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| S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW 1 PRODUCT OVERVIEW INTRODUCTION SAMSUNG's S3C44B0X 16/32-bit RISC microprocessor is designed to provide a cost-effective and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C44B0X also provides the following: 8KB cache, optional internal SRAM, LCD controller, 2-channel UART with handshake, 4channel DMA, System manager (chip select logic, FP/ EDO/SDRAM controller), 5-channel timers with PWM, I/O ports, RTC, 8-channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Sync. SIO interface and PLL for clock. The S3C44B0X was developed using a ARM7TDMI core, 0.25 um CMOS standard cells, and a memory compiler. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C44B0X adopts a new bus architecture, SAMBA II (SAMSUNG ARM CPU embedded Microcontroller Bus Architecture). An outstanding feature of the S3C44B0X is its CPU core, a 16/32-bit ARM7TDMI RISC processor (66MHz) designed by Advanced RISC Machines, Ltd. The architectural enhancements of ARM7TDMI include the Thumb decompressor, an on-chip ICE breaker debug support, and a 32-bit hardware multiplier. By providing a complete set of common system peripherals, the S3C44B0X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document are as follows: * * * * * * * * * * * * * * 2.5V Static ARM7TDMI CPU core with 8KB cache . (SAMBA II bus architecture up to 66MHz) External memory controller. (FP/EDO/SDRAM Control, Chip Select logic) LCD controller (up to 256 color DSTN) with 1-ch LCD-dedicated DMA. 2-ch general DMAs / 2-ch peripheral DMAs with external request pins 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO 1-ch multi-master IIC-BUS controller 1-ch IIS-BUS controller 5-ch PWM timers & 1-ch internal timer Watch Dog Timer 71 general purpose I/O ports / 8-ch external interrupt source Power control: Normal, Slow, Idle, and Stop mode 8-ch 10-bit ADC. RTC with calendar function. On-chip clock generator with PLL. 1-1 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR FEATURES Architecture * * * * * * Cache Memory & internal SRAM * * * * * * Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM7TDMI CPU core. Thumb de-compressor maximizes code density while maintaining performance. On-chip ICEbreaker debug support with JTAGbased debugging solution. 32x8 bit hardware multiplier. New bus architecture to implement Low-Power SAMBA II(SAMSUNG's ARM CPU embedded Micro-controller Bus Architecture). 4-way set associative ID(Unified)-cache with 8Kbyte. The 0/4/8 Kbytes internal SRAM using unused cache memory. Pseudo LRU(Least Recently Used) Replace Algorithm. Write through policy to maintain the coherence between main memory and cache content. Write buffer with four depth. Request data first fill technique when cache miss occurs. Clock & Power Manager System Manager * * * * * * * * * * Low power The on-chip PLL makes the clock for operating MCU at maximum 66MHz. Clock can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle and Stop mode. Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL Idle mode: Stop the clock for only CPU Stop mode: All clocks are stopped Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode. Little/Big endian support. Address space: 32Mbytes per each bank. (Total 256Mbyte) Supports programmable 8/16/32-bit data bus width for each bank. Fixed bank start address and programmable bank size for 7 banks. Programmable bank start address and bank size for one bank. 8 memory banks. - 6 memory banks for ROM, SRAM etc. - 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM) Fully Programmable access cycles for all memory banks. Supports external wait signal to expend the bus cycle. Supports self-refresh mode in DRAM/SDRAM for power-down. Supports asymmetric/symmetric address of DRAM. * Interrupt Controller * * * * * 30 Interrupt sources ( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO ) Vectored IRQ interrupt mode to reduce interrupt latency. Level/edge mode on the external interrupt sources Programmable polarity of edge and level Supports FIQ (Fast Interrupt request) for very urgent interrupt request * * * * FEATURES (Continued) 1-2 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Timer with PWM (Pulse Width Modulation) * DMA Controller * * * 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation. Supports external clock source. 2 channel general purpose Direct Memory Access controller without CPU intervention. 2 channel Bridge DMA (peripheral DMA) controller. Support IO to memory, memory to IO, IO to IO with the Bridge DMA which has 6 type's DMA requestor: Software, 4 internal function blocks (UART, SIO, Timer, IIS), and External pins. Programmable priority order between DMAs (fixed or round-robin mode) Burst transfer mode to enhance the transfer rate on the FPDRAM, EDODRAM and SDRAM. Supports fly-by mode on the memory to external device and external device to memory transfer mode * * * RTC (Real Time Clock) * * * * Full clock feature: msec, sec, min, hour, day, week, month, year. 32.768 KHz operation. Alarm interrupt for CPU wake-up. Time tick interrupt * * * General purpose input/output ports A/D Converter * * 8 external interrupt ports 71 multiplexed input/output ports * * 8-ch multiplexed ADC. Max. 100KSPS/10-bit. UART * * * * * * * LCD Controller * * * * * * * * 2-channel UART with DMA-based or interruptbased operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive Supports color/monochrome/gray LCD panel Supports single scan and dual scan displays Supports virtual screen function System memory is used as display memory Dedicated DMA for fetching image data from system memory Programmable screen size Gray level: 16 gray levels 256 Color levels Supports H/W handshaking during transmit/receive Programmable baud rate Supports IrDA 1.0 (115.2kbps) Loop back mode for testing Each channel have two internal 32-byte FIFO for Rx and Tx. 1-3 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR FEATURES (Continued) Watchdog Timer * * SIO (Synchronous Serial I/O) * * 16-bit Watchdog Timer Interrupt request or system reset at time-out 1-ch SIO with DMA-based or interrupt -based operation. Programmable baud rates. Supports serial data transmit/receive operations 8-bit in SIO. IIC-BUS Interface * * * 1-ch Multi-Master IIC-Bus with interrupt-based operation. Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode. * Operating Voltage Range Core : 2.5V I/O : 3.0 V to 3.6 V Operating Frequency IIS-BUS Interface * * * * Up to 66 MHz 1-ch IIS-bus for audio interface with DMA-based operation. Serial, 8/16bit per channel data transfers Supports MSB-justified data format Package * 160 LQFP / 160 FBGA 1-4 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW BLOCK DIAGRAM Bus Arbiter CPU Unit Write Buffer JTAG Boundary Scan ARM7TDMI TAP Controller ARM7TDMI CPU Core Cache 8K-byte S y s t e m B u s Memory I/F ROM/SRAM DRAM/SDRAM LCD DMA LCD CONT. Interrupt CONT. G e n e r a l P u r p o s e I / O Power Management Clock Generator (PLL) ZDMA (2-Ch) System Bus Bridge & Arbitration / BDMA (2-Ch) GPIO (Controller) AIN[7:0] ADC P e r i p h e r a l B u s I 2 C Bus Controller I2 S Bus Controller UART 0,1 (Each 16byte FIFO) Synchronout I/O PWM Timer 0-4,5 (internal) TCLK EXTCLK Watchdog Timer 32,768 Hz RTC (Real Time Clock) SIOCK Figure 1-1. S3C44B0X Block Diagram 1-5 S3C44B0X RISC MICROPROCESSOR PIN ASSIGNMENTS AIN6 AIN7 AREFT AREFB AVCOM VDDADC XTAL1 EXTAL1 VDDRTC VSSIO VFRAME/GPD7 VM/GPD6 VLINE/GPD5 VCLK/GPD4 VD3/GPD3 VD2/GPD2 VD1/GPD1 VD0/GPD0 RxD0/GPE2 TxD0/GPE1 DATA31/nCTS0/GPC15 DATA30/nRTS0/GPC14 DATA29/RxD1/GPC13 DATA28/TxD1/GPC12 DATA27/nCTS1/GPC11 DATA26/nRTS1/GPC10 DATA25/nXDREQ1/GPC9 DATA24/nXDACK1/GPC8 VDD VSS DATA23/VD4/GPC7 DATA22/VD5/GPC6 DATA21/VD6/GPC5 DATA20/VD7/GPC4 DATA19/IISCLK/GPC3 DATA18/IISDI/GPC2 DATA17/IISDO/GPC1 DATA16/IISLRCK/GPC0 DATA15 DATA14 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 VSSADC VSSIO TOUT4/VD7/GPE7 TOUT3/VD6/GPE6 TOUT2/TCLK/GPE5 TOUT1/TCLK/GPE4 TOUT0/GPE3 EXTCLK PLLCAP EXTAL0 XTAL0 VSS VDD IICSCL/GPF0 IICSDA/GPF1 SIOTxD/nRTS1/IISLRCK/GPF5 SIORDY/TxD1/IISDO/GPF6 SIORxD/RxD1/IISDI/GPF7 SIOCLK/nCTS1/IISCLK/GPF8 ENDIAN/CODECLK/GPE8 OM3 OM2 OM1 OM0 nRESET CLKout/GPE0 VSSIO VDDIO TDO TDI TMS TCK nTRST ExINT7/IISLRCK/GPG7 ExINT6/IISDO/GPG6 ExINT5/IISDI/GPG5 ExINT4/IISCLK/GPG4 ExINT3/nRTS0/GPG3 ExINT2/nCTS0/GPG2 VSS VDD ExINT1/VD5/GPG1 ExINT0/VD4/GPG0 nXDACK0/nXBACK/GPF3 nXDREQ0/nXBREQ/GPF4 nWAIT/GPF2 SCLK/GPB1 SCKE/GPB0 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 nGCS5/GPB10 nGCS4/GPB9 VSS VDD nGCS3/GPB8 nGCS2/GPB7 nGCS1/GPB6 nGCS0 nWE nOE nBE3:nWBE3:DQM3/GPB5 nBE2:nWBE2:DQM2/GPB4 nBE1:nWBE1:DQM1 nBE0:nWBE0:DQM0 VSSIO VDDIO nCAS3:nSRAS/GPB3 nCAS2:nSCAS/GPB2 nCAS1 nCAS0 ADDR0/GPA0 ADDR1 ADDR2 ADDR3 PRODUCT OVERVIEW DATA13 DATA12 DATA11 DATA10 VDDIO VSSIO DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADDR24/GPA9 VDD VSS ADDR23/GPA8 ADDR22/GPA7 ADDR21/GPA6 ADDR20/GPA5 ADDR19/GPA4 ADDR18/GPA3 ADDR17/GPA2 ADDR16/GPA1 ADDR15 ADDR14 ADDR13 ADDR12 VSSIO ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Figure 1-2. S3C44B0X Pin Assignments (160 LQFP) S3C44B0X 160-QFP 1-6 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ball Pad A1 Corner Indicator Bottom View Figure 1-3. S3C44B0X Pin Assignments (160 FBGA) 1-7 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-1. 160-Pin LQFP Pin Assignment Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ADDR3 ADDR2 ADDR1 ADDR0/GPA0 nCAS0 nCAS1 nCAS2:nSCAS/GPB2 nCAS3:nSRAS/GPB3 VDDIO VSSIO nBE0:nWBE0:DQM0 nBE1:nWBE1:DQM1 nBE2:nWBE2:DQM2/GPB4 nBE3:nWBE3:DQM3/GPB5 nOE nWE nGCS0 nGCS1/GPB6 nGCS2/GPB7 nGCS3/GPB8 VDD VSS nGCS4/GPB9 nGCS5/GPB10 nGCS6:nSCS0:nRAS0 nGCS7:nSCS1:nRAS1 SCKE/GPB0 SCLK/GPB1 nWAIT/GPF2 nXDREQ0/nXBREQ/GPF4 nXDACK0/nXBACK/GPF3 ExINT0/VD4/GPG0 ExINT1/VD5/GPG1 Pin Name Default Function ADDR3 ADDR2 ADDR1 ADDR0 nCAS0 nCAS1 nSCAS nSRAS VDDIO VSSIO DQM0 DQM1 DQM2 DQM3 nOE nWE nGCS0 nGCS1 nGCS2 nGCS3 VDD VSS nGCS4 nGCS5 nSCS0 nSCS1 SCKE SCLK GPF2 GPF4 GPF3 GPG0 GPG1 - Hi-z/O Low/O High/O - IO phot6 phot10 phbsu50ct8sm Hi-z High/High/Low Hi-z/O Hi-z/O O - - P vdd2I vss2I phot8 Hi-z/O Hi-z/O phot8 phot6 phot8 Hi-z Hi-z O - (3) - (3) P vdd3op vss3op phot6 High/Low/O Hi-z/O Hi-z Hi-z/O Low I/O State (2) @BUS REQ. Hi-z I/O State (2) @STOP Hi-z I/O State @Initial O I/O TYPE(6) phot8 1-8 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW 1-9 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-1. 160-Pin LQFP Pin Assignment (Continued) Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 VDD VSS ExINT2/nCTS0/GPG2 ExINT3/nRTS0/GPG3 ExINT4/IISCLK/GPG4 ExINT5/IISDI/GPG5 ExINT6/IISDO/GPG6 ExINT7/IISLRCK/GPG7 nTRST TCK TMS TDI TDO VDDIO VSSIO CLKout/GPE0 nRESET OM0 OM1 OM2 OM3 ENDIAN/CODECLK/GPE8 SIOCLK/nCTS1/IISCLK/GPF8 SIORxD/RxD1/IISDI/GPF7 SIORDY/TxD1/IISDO/GPF6 SIOTxD/nRTS1/IISLRCK/GPF5 IICSDA/GPF1 IICSCL/GPF0 VDD VSS XTAL0 EXTAL0 PLLCAP Pin Name Default Function VDD VSS GPG2 GPG3 GPG4 GPG5 GPG6 GPG7 nTRST TCK TMS TDI TDO VDDIO VSSIO GPE0 nRESET OM0 OM1 OM2 OM3 CODECLK GPF8 GPF7 GPF6 GPF5 GPF1 GPF0 VDD VSS XTAL0 EXTAL0 PLLCAP AI(5) AO(5) AI(5) phnc50_option P vdd2i vss2i phsoscm16 phbsu50cd4sm IO(1) phbsu50ct8sm IO I I(1) O P phot6 vdd3op vss3op phbsu50ct8sm phis I phis IO I/O State @BUS REQ. - I/O State @STOP - I/O State @Initial P I/O TYPE vdd2i vss2i phbsu50ct8sm 1-10 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 160-Pin LQFP Pin Assignment (Continued) Pin No. 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Pin Name EXTCLK TOUT0/GPE3 TOUT1/TCLK/GPE4 TOUT2/TCLK/GPE5 TOUT3/VD6/GPE6 TOUT4/VD7/GPE7 VSSIO VSSADC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AREFT AREFB AVCOM VDDADC XTAL1 EXTAL1 VDDRTC VSSIO VFRAME/GPD7 VM/GPD6 VLINE/GPD5 VCLK/GPD4 VD3/GPD3 VD2/GPD2 VD1/GPD1 VD0/GPD0 Default Function EXTCLK GPE3 GPE4 GPE5 GPE6 GPE7 VSSIO VSSADC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AREFT AREFB AVCOM VDDADC XTAL1 EXTAL1 VDDRTC VSSIO GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 IO P I O P vdd2t vss3op phbsu50ct8sm vdd2t phnc50 phnc50_option AI(5) P vss3op vss2t phnc50 I/O State @BUS REQ. - I/O State @STOP - I/O State @Initial I IO I/O TYPE phis phbsu50ct8sm 1-11 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-1. 160-Pin LQFP Pin Assignment (Continued) Pin No. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Pin Name RxD0/GPE2 TxD0/GPE1 DATA31/nCTS0/GPC15 DATA30/nRTS0/GPC14 DATA29/RxD1/GPC13 DATA28/TxD1/GPC12 DATA27/nCTS1/GPC11 DATA26/nRTS1/GPC10 DATA25/nXDREQ1/GPC9 DATA24/nXDACK1/GPC8 VDD VSS DATA23/VD4/GPC7 DATA22/VD5/GPC6 DATA21/VD6/GPC5 DATA20/VD7/GPC4 DATA19/IISCLK/GPC3 DATA18/IISDI/GPC2 DATA17/IISDO/GPC1 DATA16/IISLRCK/GPC0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 VDDIO VSSIO DATA9 DATA8 DATA7 DATA6 Default Function GPE2 GPE1 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 VDD VSS DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 VDDIO VSSIO DATA9 DATA8 DATA7 DATA6 Hi-z Hi-z I(Hi-z) - - P vdd3op vss3op phbsu50ct12sm Hi-z Hi-z I(Hi-z) Hi-z/IO Hi-z/IO I(Hi-z) - - P vdd2i vss2i phbsu50ct12sm Hi-z/IO Hi-z/IO I(Hi-z) phbsu50ct12sm I/O State @BUS REQ. - I/O State @STOP - I/O State @Initial IO I/O TYPE phbsu50ct8sm 1-12 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 160-Pin LQFP Pin Assignment (Concluded) Pin No. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADDR24/GPA9 VDD VSS ADDR23/GPA8 ADDR22/GPA7 ADDR21/GPA6 ADDR20/GPA5 ADDR19/GPA4 ADDR18/GPA3 ADDR17/GPA2 ADDR16/GPA1 ADDR15 ADDR14 ADDR13 ADDR12 VSSIO ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 Default Function DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADDR24 VDD VSS ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 DATA16 ADDR15 ADDR14 ADDR13 ADDR12 VSSIO ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 - Hi-z - Hi-z P O vss3op phot8 Hi-z Hi-z Hi-z/O Hi-z/O O Hi-z/O - Hi-z/O - O P phot8 vdd2i vss2i phot8 I/O State @BUS REQ. Hi-z I/O State @STOP Hi-z I/O State @Initial I(Hi-z) I/O TYPE phbsu50ct12sm 1-13 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-2. 160-Pin FBGA Pin Assignment Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 ADDR4 ADDR5 ADDR6 ADDR10 ADDR13 ADDR17/GPA2 ADDR20/GPA5 ADDR23/GPA8 DATA0 DATA4 DATA8 DATA11 DATA12 DATA14 ADDR2 ADDR3 ADDR7 ADDR9 ADDR12 ADDR16/GPA1 ADDR19/GPA4 VSS DATA1 DATA5 DATA9 DATA10 DATA13 DATA15 Pin Name Pin No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 ADDR1 ADDR0/GPA0 nCAS0 ADDR8 VSSIO ADDR15 ADDR21/GPA6 ADDR22/GPA7 ADDR24/GPA9 DATA3 DATA7 VDDIO DATA17/IISDO/GPC1 DATA16/IISLRCK/GPC0 nCAS3:nSRAS/GPB3 nCAS2:nSCAS/GPB2 VDDIO nCAS1 ADDR11 ADDR14 ADDR18/GPA3 VDD DATA2 DATA6 VSSIO DATA18/IISDI/GPC2 DATA19/IISCLK/GPC3 DATA20/VD7/GPC4 Pin Name 1-14 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. 160-Pin FBGA Pin Assignment (Continued) Pin No. E1 E2 E3 E4 E11 E12 E13 E14 F1 F2 F3 F4 F11 F12 F13 F14 G1 G2 G3 G4 G11 G12 G13 G14 Pin Name nBE1:nWBE1:DQM1 nBE0:nWBE0:DQM0 nBE2:nWBE2:DQM2/GPB4 VSSIO DATA21/VD6/GPC5 DATA22/VD5/GPC6 DATA23/VD4/GPC7 VSS nWE nOE nGCS0 nBE3:nWBE3:DQM3/GPB5 VDD DATA24/nXDACK1/GPC8 DATA25/nXDREQ1/GPC9 DATA26/nRTS1/GPC10 nGCS3/GPB8 nGCS2/GPB7 VDD nGCS1/GPB6 DATA27/nCTS1/GPC11 DATA30/nRTS0/GPC14 DATA28/TxD1/GPC12 DATA29/RxD1/GPC13 Pin No. H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 K4 K11 K12 K13 K14 nGCS4/GPB9 nGCS5/GPB10 VSS nGCS6:nSCS0:nRAS0 VD0/GPD0 DATA31/nCTS0/GPC15 RxD0/GPE2 TxD0/GPE1 nGCS7:nSCS1:nRAS1 SCKE/GPB0 SCLK/GPB1 nWAIT/GPF2 VCLK/GPD4 VD1/GPD1 VD3/GPD3 VD2/GPD2 nXDREQ0/nXBREQ0/GPF4 nXDACK0/nXBACK0/GPF3 ExINT0/VD4/GPG0 ExINT1/VD5/GPG1 VSSIO VLINE/GPD5 VFRAME/GPD7 VM/GPD6 Pin Name 1-15 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-2. 160-Pin FBGA Pin Assignment (Continued) Pin No. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 VDD VSS ExINT2/nCTS0/GPG2 TDO nRESET OM3 SIORDY/TxD1/IISDO/GPF6 EXTAL0 TOUT1/TCLK/GPE4 VSSIO VDDADC VDDRTC XTAL1 EXTAL1 ExINT4/IISCLK/GPG4 ExINT3/nRTS0/GPG3 TDI CLKout/GPE0 OM2 SIORxD/RxD1/IISDI/GPF7 IICSCL/GPF0 VDD TOUT0/GPE3 TOUT4/VD7/GPE7 AIN1 AVCOM AREFB AREFT Pin Name Pin No. N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Pin Name ExINT5/IISDI/GPG5 ExINT7/IISLRCK/GPG7 TMS VDDIO OM0 ENDIAN/CODECLK/GPE8 SIOTxD/nRTS1/IISLRCK/GPF5 XTAL0 EXTCLK TOUT3/VD6/GPE6 AIN0 AIN2 AIN6 AIN7 ExINT6/IISDO/GPG6 nTRST TCK VSSIO OM1 SIOCLK/nCTS1/IISCLK/GPF8 IICSDA/GPF1 VSS PLLCAP TOUT2/TCLK/GPE5 VSSADC AIN3 AIN4 AIN5 NOTES : 1. OM[3:0] and ENDIAN value are latched only at the rising edge of nRESET. Therefore, when nRESET is L, the pins of OM[3:0] and ENDIAN are in input state. After nRESET becomes H, the pin of ENDIAN will be in output state. 2. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master. The @STOP shows the pin states when S3C44B0X is in STOP mode. 3. ' - ' mark indicates the unchanged pin state at STOP mode or Bus released mode. 4. IICSDA,IICSCL pins are open-drain type. 5. AI/AO means analog input/output. 1-16 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW I/O Type vdd2i, vss2i vdd3op, vss3op vdd2t, vss2t phsoscm16 phbsu50ct12sm phbsu50ct8sm phbsu50cd4sm phot6 phot8 phot10 phis phnc50, phnc50_option 2.5V Vdd/Vss for internal logic Descriptions 3.3V Vdd/Vss for external interface logic 2.5V Vdd/Vss for analog circuitry Oscillator cell with enable and feedback resistor bi-directional pad, CMOS schmitt-trigger, 50K pull-up resistor with control, tri-state, Io=12mA bi-directional pad, CMOS schmitt-trigger, 50K pull-up resistor with control, tri-state, Io=8mA bi-directional pad, CMOS schmitt-trigger, 50K pull-up resistor with control, tri-state, Io=4mA output pad, tri-state, Io=6mA output pad, tri-state, Io=8mA output pad, tri-state, Io=10mA input pad, CMOS schmitt-trigger pad for analog pin 1-17 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR SIGNAL DESCRIPTIONS Table 1-3. S3C44B0X Signal Descriptions Signal BUS CONTROLLER OM[1:0] I OM[1:0] sets S3C44B0X in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The logic level is determined by the pull-up/down resistor during the RESET cycle. 00:8-bit ADDR[24:0] DATA[31:0] nGCS[7:0] O IO O 01:16-bit 10:32-bit 11:Test mode I/O Description ADDR[24:0] (Address Bus) outputs the memory address of the corresponding bank . DATA[31:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16/32-bit. nGCS[7:0] (General Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. nWE (Write Enable) indicates that the current bus cycle is a write cycle. Write Byte Enable Upper Byte/Lower Byte Enable(In case of SRAM) nOE (Output Enable) indicates that the current bus cycle is a read cycle. nXBREQ (Bus Hold Request) allows another bus master to request control of the local bus. BACK active indicates that bus control has been granted. nXBACK (Bus Hold Acknowledge) indicates that the S3C44B0X has surrendered control of the local bus to another bus master. nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus cycle cannot be completed. It determines whether or not the data type is little endian or big endian. The logic level is determined by the pull-up/down resistor during the RESET cycle. 0:little endian 1:big endian nWE nWBE[3:0] nBE[3:0] nOE nXBREQ nXBACK nWAIT ENDIAN O O O O I O I I DRAM/SDRAM/SRAM nRAS[1:0] nCAS[3:0] nSRAS nSCAS nSCS[1:0] DQM[3:0] SCLK SCKE O O O O O O O O Row Address Strobe Column Address strobe SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Chip Select SDRAM Data Mask SDRAM Clock SDRAM Clock Enable 1-18 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. S3C44B0X Signal Descriptions (Continued) Signal I/O Description LCD CONTROL UNIT VD[7:0] VFRAME VM VLINE VCLK TIMER/PWM TOUT[4:0] TCLK O I Timer output[4:0] External clock input O O O O O LCD Data Bus LCD Frame signal VM alternates the polarity of the row and column voltage LCD line signal LCD clock signal INTERRUPT CONTROL UNIT EINT[7:0] DMA nXDREQ[1:0] nXDACK[1:0] UART RxD[1:0] TxD[1:0] nCTS[1:0] nRTS[1:0] IIC-BUS IICSDA IICSCL IIS-BUS IISLRCK IISDO IISDI IISCLK CODECLK SIO SIORXD SIOTXD SIOCK SIORDY I O IO IO SIO receives data input SIO transmits data output SIO clock SIO handshake signal when DMA completes the SIO operation IO O I IO O IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock IO IO IIC-bus data IIC-bus clock I O I O UART receives data input UART transmits data output UART clear to send input signal UART request to send output signal I O External DMA request External DMA acknowledge I External Interrupt request 1-19 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-3. S3C44B0X Signal Descriptions (Continued) Signal ADC AIN[7:0] AREFT AREFB AVCOM GENERAL PORT P[70:0] RESET & CLOCK nRESET ST nRESET suspends any operation in progress and places S3C44B0X into a known reset state. For a reset, nRESET must be held to L level for at least 4 MCLK after the processor power has been stabilized. OM[3:2] determines how the clock is made. 00 = Crystal(XTAL0,EXTAL0), PLL on 10, 11 = Chip test mode. EXTCLK XTAL0 EXTAL0 PLLCAP XTAL1 EXTAL1 CLKout JTAG TEST LOGIC nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger(black ICE) is not used, nTRST pin must be at L or low active pulse. TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor must be connected to TCK pin. TDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor must be connected to TDI pin. TDO (TAP Controller Data Output) is the serial output for test instructions and data. I AI AO AI AI AO O 01 = EXTCLK, PLL on IO General input/output ports (some ports are output mode only) AI AI AI AI ADC input[7:0] ADC Top Vref ADC Bottom Vref ADC Common Vref I/O Description OM[3:2] I External clock source when OM[3:2] = 01b If it isn't used, it has to be H (3.3V). Crystal Input for internal osc circuit for system clock. If it isn't used, XTAL0 has to be H (3.3V). Crystal Output for internal osc circuit for system clock. It is the inverted output of XTAL0. If it isn't used, it has to be a floating pin. Loop filter capacitor for system clock PLL. ( 700pF ) 32 KHz crystal input for RTC. 32 KHz crystal output for RTC. It is the inverted output of XTAL1. Fout or Fpllo clock TMS TCK TDI TDO I I I O 1-20 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. S3C44B0X Signal Descriptions (Concluded) Signal POWER VDD VSS VDDIO VSSIO RTCVDD VDDADC VSSADC P P P P P P P S3C44B0X core logic VDD (2.5 V) S3C44B0X core logic VSS S3C44B0X I/O port VDD (3.3 V) S3C44B0X I/O port VSS RTC VDD (2.5 V or 3.0 V, Not support 3.3V) (This pin must be connected to power properly if RTC isn't used) ADC VDD(2.5 V) ADC VSS I/O Description 1-21 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR S3C44B0X SPECIAL REGISTERS Table 1-4. S3C44B0X Special Registers Register Name CPU WRAPPER SYSCFG NCACHBE0 NCACHBE1 SBUSCON 0x01c00000 0x01c00004 0x01c00008 0x01c40000 W R/W System Configuration Non Cacheable Area 0 Non Cacheable Area 1 System Bus Control Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function MEMORY CONTROLLER BWSCON BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 BANKCON6 BANKCON7 REFRESH BANKSIZE MRSRB6 MRSRB7 0x01c80000 0x01c80004 0x01c80008 0x01c8000c 0x01c80010 0x01c80014 0x01c80018 0x01c8001c 0x01c80020 0x01c80024 0x01c80028 0x01c8002c 0x01c80030 W R/W Bus Width & Wait Status Control Boot ROM Control BANK1 Control BANK2 Control BANK3 Control BANK4 Control BANK5 Control BANK6 Control BANK7 Control DRAM/SDRAM Refresh Control Flexible Bank Size Mode register set for SDRAM Mode register set for SDRAM 1-22 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C44B0X Special Registers (Continued) Register Name UART ULCON0 ULCON1 UCON0 UCON1 UFCON0 UFCON1 UMCON0 UMCON1 UTRSTAT0 UTRSTAT1 UERSTAT0 UERSTAT1 UFSTAT0 UFSTAT1 UMSTAT0 UMSTAT1 UTXH0 UTXH1 URXH0 URXH1 UBRDIV0 UBRDIV1 SIO SIOCON SIODAT SBRDR ITVCNT DCNTZ 0x01d14000 0x01d14004 0x01d14008 0x01d1400c 0x01d14010 Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function 0x01d00000 0x01d04000 0x01d00004 0x01d04004 0x01d00008 0x01d04008 0x01d0000c 0x01d0400c 0x01d00010 0x01d04010 0x01d00014 0x01d04014 0x01d00018 0x01d04018 0x01d0001c 0x01d0401c 0x01d00023 0x01d04023 0x01d00027 0x01d04027 0x01d00028 0x01d04028 W R/W UART 0 Line Control UART 1 Line Control UART 0 Control UART 1 Control UART 0 FIFO Control UART 1 FIFO Control UART 0 Modem Control UART 1 Modem Control R UART 0 Tx/Rx Status UART 1 Tx/Rx Status UART 0 Rx Error Status UART 1 Rx Error Status UART 0 FIFO Status UART 1 FIFO Status UART 0 Modem Status UART 1 Modem Status 0x01d00020 0x01d04020 0x01d00024 0x01d04024 B W UART 0 Transmission Hold UART 1 Transmission Hold R UART 0 Receive Buffer UART 1 Receive Buffer W R/W UART 0 Baud Rate Divisor UART 1 Baud Rate Divisor W R/W SIO Control SIO Data SIO Baud Rate Prescaler SIO Interval Counter SIO DMA Count Zero 1-23 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-4. S3C44B0X Special Registers (Continued) Register Name IIS IISCON IISMOD IISPSR IISFIFCON IISFIF I/O PORT PCONA PDATA PCONB PDATB PCONC PDATC PUPC PCOND PDATD PUPD PCONE PDATE PUPE PCONF PDATF PUPF PCONG PDATG PUPG SPUCR EXTINT EXTINPND 0x01d20000 0x01d20004 0x01d20008 0x01d2000c 0x01d20010 0x01d20014 0x01d20018 0x01d2001c 0x01d20020 0x01d20024 0x01d20028 0x01d2002c 0x01d20030 0x01d20034 0x01d20038 0x01d2003c 0x01d20040 0x01d20044 0x01d20048 0x01d2004c 0x01d20050 0x01d20054 Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function 0x01d18000,02,03 0x01d18004,06 0x01d18008,0a,0b 0x01d1800c,0e 0x01d18012 0x01d18000 0x01d18004 0x01d18008 0x01d1800c 0x01d18010 B,HW,W HW,W B,HW,W HW,W HW R/W IIS Control IIS Mode IIS Prescaler IIS FIFO Control IIS FIFO Entry W R/W Port A Control Port A Data Port B Control Port B Data Port C Control Port C Data Pull-up Control C Port D Control Port D Data Pull-up Control D Port E Control Port E Data Pull-up Control E Port F Control Port F Data Pull-up Control F Port G Control Port G Data Pull-up Control G Special Pull-up External Interrupt Control External Interrupt Pending WATCHDOG TIMER WTCON WTDAT WTCNT 0x01d30000 0x01d30004 0x01d30008 W R/W Watchdog Timer Mode Watchdog Timer Data Watchdog Timer Count 1-24 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C44B0X Special Registers (Continued) Register Name A/D CONVERTER ADCCON ADCPSR ADCDAT PWM TIMER TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCMPB4 TCNTO4 TCNTB5 TCNTO5 IIC IICCON IICSTAT IICADD IICDS 0x01d60000 0x01d60004 0x01d60008 0x01d6000c Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function 0x01d40000,02,03 0x01d40004,06,07 0x01d40008,0a 0x01d40000 0x01d40004 0x01d40008 B,HW,W R/W ADC Control ADC Prescaler HW,W R Digitized 10 bit Data 0x01d50000 0x01d50004 0x01d50008 0x01d5000c 0x01d50010 0x01d50014 0x01d50018 0x01d5001c 0x01d50020 0x01d50024 0x01d50028 0x01d5002c 0x01d50030 0x01d50034 0x01d50038 0x01d5003c 0x01d50040 0x01d50044 0x01d50048 0x01d5004c W R/W Timer Configuration Timer Configuration Timer Control Timer Count Buffer 0 Timer Compare Buffer 0 R R/W Timer Count Observation 0 Timer Count Buffer 1 Timer Compare Buffer 1 R R/W Timer Count Observation 1 Timer Count Buffer 2 Timer Compare Buffer 2 R R/W Timer Count Observation 2 Timer Count Buffer 3 Timer Compare Buffer 3 R R/W Timer Count Observation 3 Timer Count Buffer 4 Timer Compare Buffer 4 R R/W R Timer Count Observation 4 Timer Count Buffer 5 Timer Count Observation 5 W R/W IIC Control IIC Status IIC Address IIC Data Shift 1-25 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-4. S3C44B0X Special Registers (Continued) Register Name RTC RTCCON RTCALM ALMSEC ALMMIN ALMHOUR ALMDAY ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON BCDYEAR TICINT 0x01d70043 0x01d70053 0x01d70057 0x01d7005b 0x01d7005f 0x01d70063 0x01d70067 0x01d7006b 0x01d7006f 0x01d70073 0x01d70077 0x01d7007b 0x01d7007f 0x01d70083 0x01d70087 0x01d7008b 0x01D7008E 0x01d70040 0x01d70050 0x01d70054 0x01d70058 0x01d7005c 0x01d70060 0x01d70064 0x01d70068 0x01d7006c 0x01d70070 0x01d70074 0x01d70078 0x01d7007c 0x01d70080 0x01d70084 0x01d70088 0x01D7008C B R/W RTC Control RTC Alarm Alarm Second Alarm Minute Alarm Hour Alarm Day Alarm Month Alarm Year RTC Round Reset BCD Second BCD Minute BCD Hour BCD Day BCD Date BCD Month BCD Year Tick time count Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function CLOCK & POWER MANAGEMENT PLLCON CLKCON CLKSLOW LOCKTIME 0x01d80000 0x01d80004 0x01d80008 0x01d8000c W R/W PLL Control Clock Control Slow clock Control PLL lock time Counter 1-26 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-4. S3C44B0X Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function INTERRUPT CONTROLLER INTCON INTPND INTMOD INTMSK I_PSLV I_PMST I_CSLV I_CMST I_ISPR I_ISPC F_ISPR F_ISPC 0x01e00000 0x01e00004 0x01e00008 0x01e0000c 0x01e00010 0x01e00014 0x01e00018 0x01e0001c 0x01e00020 0x01e00024 0x01e00038 0x01e0003c W R/W R R/W Interrupt Control Interrupt Request Status Interrupt Mode Control Interrupt Mask Control IRQ Interrupt Previous Slave IRQ Interrupt Priority Master R IRQ Interrupt Current Slave IRQ Interrupt Current Master IRQ Interrupt Pending Status W R W IRQ Interrupt Pending Clear FIQ Interrupt Pending FIQ Interrupt Pending Clear LCD CONTROLLER LCDCON1 LCDCON2 LCDCON3 LCDSADDR1 LCDSADDR2 LCDSADDR3 REDLUT GREENLUT BLUELUT DP1_2 DP4_7 DP3_5 DP2_3 DP5_7 DP3_4 DP4_5 DP6_7 DITHMODE 0x01f00000 0x01f00004 0x01f00040 0x01f00008 0x01f0000c 0x01f00010 0x01f00014 0x01f00018 0x01f0001c 0x01f00020 0x01f00024 0x01f00028 0x01f0002c 0x01f00030 0x01f00034 0x01f00038 0x01f0003c 0x01f00044 W R/W LCD Control 1 LCD Control 2 LCD Control 3 Frame Upper Buffer Start Address 1 Frame Lower Buffer Start Address 2 Virtual Screen Address RED Lookup Table GREEN Lookup Table BLUE Lookup Table Dithering Pattern duty 1/2 Dithering Pattern duty 4/7 Dithering Pattern duty 3/5 Dithering Pattern duty 2/3 Dithering Pattern duty 5/7 Dithering Pattern duty 3/4 Dithering Pattern duty 4/5 Dithering Pattern duty 6/7 Dithering Mode 1-27 PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR Table 1-4. S3C44B0X Special Registers (Concluded) Register Name DMA ZDCON0 ZDISRC0 ZDIDES0 ZDICNT0 ZDCSRC0 ZDCDES0 ZDCCNT0 ZDCON1 ZDISRC1 ZDIDES1 ZDICNT1 ZDCSRC1 ZDCDES1 ZDCCNT1 BDCON0 BDISRC0 BDIDES0 BDICNT0 BDCSRC0 BDCDES0 BDCCNT0 BDCON1 BDISRC1 BDIDES1 BDICNT1 BDCSRC1 BDCDES1 BDCCNT1 0x01e80000 0x01e80004 0x01e80008 0x01e8000c 0x01e80010 0x01e80014 0x01e80018 0x01e80020 0x01e80024 0x01e80028 0x01e8002c 0x01e80030 0x01e80034 0x01e80038 0x01f80000 0x01f80004 0x01f80008 0x01f8000c 0x01f80010 0x01f80014 0x01f80018 0x01f80020 0x01f80024 0x01f80028 0x01f8002c 0x01f80030 0x01f80034 0x01f80038 R R/W R R/W R R/W R W R/W ZDMA0 Control ZDMA 0 Initial Source Address ZDMA 0 Initial Destination Address ZDMA 0 Initial Transfer Count ZDMA 0 Current Source Address ZDMA 0 Current Destination Address ZDMA 0 Current Transfer Count ZDMA 1 Control ZDMA 1 Initial Source Address ZDMA 1 Initial Destination Address ZDMA 1 Initial Transfer Count ZDMA 1 Current Source Address ZDMA 1 Current Destination Address ZDMA 1 Current Transfer Count BDMA 0 Control BDMA 0 Initial Source Address BDMA 0 Initial Destination Address BDMA 0 Initial Transfer Count BDMA 0 Current Source Address BDMA 0 Current Destination Address BDMA 0 Current Transfer Count BDMA 1 Control BDMA 1 Initial Source Address BDMA 1 Initial Destination Address BDMA 1 Initial Transfer Count BDMA 1 Current Source Address BDMA 1 Current Destination Address BDMA 1 Current Transfer Count Address (B. Endian) Address (L. Endian) Acc. Unit Read/W rite Function 1-28 S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW IMPORTANT NOTES ABOUT S3C44B0X SPECIAL REGISTERS 1. 2. 3. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be used. The special registers have to be accessed by the recommended access unit. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian. 4. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used. 5. W: 32-bit register, which must be accessed by LDR/STR or int type pointer(int *). HW: 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B: 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char *). 1-29 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL 2 OVERVIEW * * PROGRAMMER'S MODEL S3C44B0X has been developed using the advanced ARM7TDMI core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM7TDMI can be in one of two states: ARM state which executes 32-bit, word-aligned ARM instructions. THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate halfwords. NOTE Transition between these two states does not affect the processor mode or the contents of the registers. SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register. Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state. Entering ARM State Entry into ARM state happens: * * On execution of the BX instruction with the state bit clear in the operand register. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is placed in the exception mode's link register, and execution commences at the exception's vector address. MEMORY FORMATS ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words in memory as being stored either in Big-Endian or Little-Endian format. 2-1 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24. Higher Address 31 8 4 0 Lower Address 24 23 9 5 1 16 15 10 6 2 8 7 11 7 3 0 Word Address 8 4 0 Most significant byte is at lowest address. Word is addressed by byte address of most significant byte. Figure 2-1. Big-Endian Addresses of Bytes within Words LITTLE-ENDIAN FORMAT In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0. Higher Address 31 11 7 3 Lower Address 24 23 10 6 2 16 15 9 5 1 8 7 8 4 0 0 Word Address 8 4 0 Least significant byte is at lowest address. Word is addressed by byte address of least significant byte. Figure 2-2. Little-Endian Addresses of Bytes whthin Words INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). Data Types ARM7TDMI supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries. 2-2 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL OPERATING MODES ARM7TDMI supports seven modes of operation: * * * * * * * User (usr): The normal ARM program execution state FIQ (fiq): Designed to support a data transfer or channel process IRQ (irq): Used for general-purpose interrupt handling Supervisor (svc): Protected mode for the operating system Abort mode (abt): Entered after a data or instruction prefetch abort System (sys): A privileged user mode for the operating system Undefined (und): Entered when an undefined instruction is executed Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources. REGISTERS ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer. The ARM State Register Set In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information. Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch and Link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines. holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC. is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits. Register 15 Register 16 FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers. 2-3 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR ARM State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC) Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) Abort R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC) ARM State Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und = banked register Figure 2-3. Register Organization in ARM State 2-4 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4. THUMB State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC FIQ R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC Supervisor R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc PC Abort R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC IRQ R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC Undefined R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC THUMB State Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und = banked register Figure 2-4. Register Organization in THUMB State 2-5 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way: * * * * * THUMB state R0-R7 and ARM state R0-R7 are identical THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state Program Counter maps onto the ARM state Program Counter (R15) This relationship is shown in Figure 2-5. THUMB state R0 R1 R2 R3 R4 R5 R6 R7 ARM state R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Stack Pointer (R13) Link register (R14) Program Counter (R15) CPSR SPSR Stack Pointer (SP) Link register (LR) Program Counter (PC) CPSR SPSR Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers 2-6 Hi-registers Lo-registers S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34. THE PROGRAM STATUS REGISTERS The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register's functions are: * * * Hold information about the most recently performed ALU operation Control the enabling and disabling of interrupts Set the processor operating mode The arrangement of bits is shown in Figure 2-6. Condition Code Flags 31 N 30 Z 29 C 28 V 27 26 (Reserved) 25 24 23 ~ ~ I ~ ~ Overflow Carry/Borrow/Extend Zero Negative/Less Than F T 8 7 6 5 Control Bits 4 M4 3 M3 2 M2 1 M1 0 M0 Mode bits State bit FIQ disable IRQ disable Figure 2-6. Program Status Register Format 2-7 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details. The Control Bits The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software. The T bit This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal. Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state. Interrupt disable bits The mode bits The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively. The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied. The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. Reserved bits 2-8 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL Table 2-1. PSR Mode Bit Values M[4:0] 10000 User Mode Visible THUMB state registers R7..R0, LR, SP PC, CPSR R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0, LR_irq, SP_irq PC, CPSR, SPSR_irq R7..R0, LR_svc, SP_svc, PC, CPSR, SPSR_svc R7..R0, LR_abt, SP_abt, PC, CPSR, SPSR_abt R7..R0 LR_und, SP_und, PC, CPSR, SPSR_und R7..R0, LR, SP PC, CPSR Visible ARM state registers R14..R0, PC, CPSR R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq R12..R0, R14_svc, R13_svc, PC, CPSR, SPSR_svc R12..R0, R14_abt, R13_abt, PC, CPSR, SPSR_abt R12..R0, R14_und, R13_und, PC, CPSR R14..R0, PC, CPSR 10001 FIQ 10010 IRQ 10011 Supervisor 10111 Abort 11011 Undefined 11111 System Reserved bits The remaining bits in the PSR's are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. 2-9 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-14. Action on Entering an Exception When handling an exception, the ARM7TDMI: 1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state. 2. Copies the CPSR into the appropriate SPSR 3. Forces the CPSR mode bits to a value which depends on the exception 4. Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the PC is loaded with the exception vector address. Action on Leaving an Exception On completion, the exception handler: 1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.) 2. Copies the SPSR back to the CPSR 3. Clears the interrupt disable flags, if they were set on entry NOTE An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception. 2-10 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL Exception Entry/Exit Summary Table 2-2 summarises the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction BL SWI UDEF FIQ IRQ PABT DABT RESET MOV PC, R14 MOVS PC, R14_svc MOVS PC, R14_und SUBS PC, R14_fiq, #4 SUBS PC, R14_irq, #4 SUBS PC, R14_abt, #4 SUBS PC, R14_abt, #8 NA PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 8 - Previous State ARM R14_x THUMB R14_x PC + 2 PC + 2 PC + 2 PC + 4 PC + 4 PC + 4 PC + 8 - 1 1 1 2 2 1 3 4 Notes NOTES: 1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort. 2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority. 3. Where PC is the address of the Load or Store instruction which generated the data abort. 4. The value saved in R14_svc upon reset is unpredictable. FIQ The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimising the overhead of context switching). FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing SUBS PC,R14_fiq,#4 FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction. 2-11 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode. Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing SUBS Abort An abort indicates that the current memory access cannot be completed. It can be signalled by the external ABORT input. ARM7TDMI checks for the abort exception during memory access cycles. There are two types of abort: * * PC,R14_irq,#4 Prefetch abort: occurs during an instruction prefetch. Data abort: occurs during a data access. If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. If a data abort occurs, the action taken depends on the instruction type: * * * Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware of this. The swap instruction (SWP) is aborted as though it had not been executed. Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction. The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb): SUBS SUBS PC,R14_abt,#4 PC,R14_abt,#8 ; for a prefetch abort, or ; for a data abort This restores both the PC and the CPSR, and retries the aborted instruction. 2-12 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL Software Interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI. NOTE nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM7TDMI CPU core. Undefined Instruction When ARM7TDMI comes across an instruction which it cannot handle, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation. After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb): MOVS PC,R14_und This restores the CPSR and returns to the instruction following the undefined instruction. Exception Vectors The following table shows the exception vector addresses. Table 2-3. Exception Vectors Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Reset Undefined instruction Software Interrupt Abort (prefetch) Abort (data) Reserved IRQ FIQ Exception Undefined Supervisor Abort Abort Reserved IRQ FIQ Mode in Entry Supervisor 2-13 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR Exception Priorites When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt. Not All Exceptions Can Occur at Once: Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decodings of the current instruction. If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM7TDMI enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations. 2-14 S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM7TDMI will be executing the instruction at 0x1C. Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser (Tsyncmin) plus Tfiq. This is 4 processor cycles. RESET When the nRESET signal goes LOW, ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM7TDMI: 1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined. 2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit. 3. Forces the PC to fetch the next instruction from address 0x00. 4. Execution resumes in ARM state. 2-15 PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR NOTES 2-16 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET 3 INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core. FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond 00I Opcode S Rn Rd RdHi Rn Rd Rn RdLo Rd Operand2 Rs Rn 1001 1001 Rm Rm Rm Rn Rm Offset Data/Processing/ PSR Transfer Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer: register offset Halfword Data Transfer: immendiate offset Single Data Transfer 1 Rn Offset Rn CRn CRn CRd CRd Rd CP# CP# CP# CP CP Offset 0 1 CRm CRm Register List Undefined Block Data Transfer Branch Coprocessor Data Transfer Coprocessor Data Operation Coprocessor Register Transfer Software Interrupt 0 00000AS 0 0 00 1UAS 0 0010B00 00001001 000100101111111111110001 0 0 0 PU0WL 0 0 0 PU1WL 0 1 I P U BWL 01I 1 0 0 P U BWL 101L 1 1 0 P U BWL 1110 1110 1111 CP Opc CP Opc L Rn Rn Rn Rd Rd Rd 00001SH1 Offset 1SH1 Offset Ignored by processor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 3-1. ARM Instruction Set Format 3-1 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations. INSTRUCTION SUMMARY Table 3-1. The ARM Instruction Set Mnemonic ADC ADD AND B BIC BL BX CDP CMN CMP EOR LDC LDM LDR MCR MLA MOV Add with carry Add AND Branch Bit Clear Branch with Link Branch and Exchange Coprocessor Data Processing Compare Negative Compare Exclusive OR Load coprocessor from memory Load multiple registers Load register from memory Move CPU register to coprocessor register Multiply Accumulate Move register or constant Instruction Rd: = Rn + Op2 Rd: = Rn AND Op2 R15: = address Rd: = Rn AND NOT Op2 R14: = R15, R15: = address R15: = Rn, T bit: = Rn[0] (Coprocessor-specific) CPSR flags: = Rn + Op2 CPSR flags: = Rn - Op2 Rd: = (Rn AND NOT Op2) OR (Op2 AND NOT Rn) Coprocessor load Stack manipulation (Pop) Rd: = (address) cRn: = rRn { 3-2 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3-1. The ARM Instruction Set (Continued) Mnemonic MRC MRS MSR MUL MVN ORR RSB RSC SBC STC STM STR SUB SWI SWP TEQ TST Instruction Move from coprocessor register to CPU register Move PSR status/flags to register Move register to PSR status/flags Multiply Move negative register OR Reverse Subtract Reverse Subtract with Carry Subtract with Carry Store coprocessor register to memory Store Multiple Store register to memory Subtract Software Interrupt Swap register with memory Test bitwise equality Test bits Action Rn: = cRn { 3-3 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which means the Branch will only be taken if the Z flag is set. In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved, and must not be used. In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes. Table 3-2. Condition Code Summary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Suffix EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N not equal to V Z clear AND (N equals V) Z set OR (N not equal to V) (ignored) Flags equal not equal unsigned higher or same unsigned lower negative positive or zero overflow no overflow unsigned higher unsigned lower or same greater or equal less than greater than less than or equal always Meaning 3-4 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions. 31 Cond 28 27 24 23 20 19 16 15 12 11 87 43 Rn 0 000100101111111111110001 [3:0] Operand Register If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions [31:28] Condition Field Figure 3-2. Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively. ASSEMBLER SYNTAX BX - branch and exchange. BX {cond} Rn {cond} Rn Two character condition mnemonic. See Table 3-2. is an expression evaluating to a valid register number. USING R15 AS AN OPERAND If R15 is used as an operand, the behavior is undefined. 3-5 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR Examples ADR R0, Into_THUMB + 1 ; ; ; ; ; ; ; Generate branch target address and set bit 0 high - hence arrive in THUMB state. Branch and change to THUMB state. Assemble subsequent code as THUMB instructions BX CODE16 Into_THUMB * * * R0 ADR R5, Back_to_ARM BX R5 * * * ; Generate branch target to word aligned address ; - hence bit 0 is low and so change back to ARM state. ; Branch and change back to ARM state. ALIGN CODE32 Back_to_ARM ; Word align ; Assemble subsequent code as ARM instructions 3-6 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. 31 Cond 28 27 101 25 24 23 L Offset 0 [24] Link bit 0 = Branch 1 = Branch with link [31:28] Condition Field Figure 3-3. Branch Instructions Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction. Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required. THE LINK BIT Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared. To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn. INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential (S-cycle) and internal (I-cycle). 3-7 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR ASSEMBLER SYNTAX Items in {} are optional. Items in <> must be present. B{L}{cond} EXAMPLES here BAL B CMP BEQ BL ADDS BLCC here there R1,#0 fred sub+ROM R1,#1 sub ; ; ; ; ; ; ; ; ; ; Assembles to 0xEAFFFFFE (note effect of PC offset). Always condition used as default. Compare R1 with zero and branch to fred if R1 was zero, otherwise continue. Continue to next instruction. Call subroutine at computed address. Add 1 to register 1, setting CPSR flags on the result then call subroutine if the C flag is clear, which will be the case unless R1 held 0xFFFFFFFF. 3-8 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 31 Cond 28 27 26 25 24 00 L 21 20 19 S Rn 16 15 Rd 12 11 Operand2 0 OpCode [15:12] Destination register 0 = Branch 1 = Branch with link [19:16] 1st operand register 0 = Branch 1 = Branch with link [20] Set condition codes 0 = Do not after condition codes 1 = Set condition codes [24:21] Operation codes 0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-1 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =Op2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2 [25] Immediate operand 0 = Operand 2 is a register 1 = Operand 2 is an immediate value [11:0] Operand 2 type selection 11 Shift [3:0] 2nd operand register 11 Rotate 87 Imm [11:8] Shift applied to Imm 0 34 Rm [11:4] Shift applied to Rm 0 [7:0] Unsigned 8 bit immediate value [31:28] Condition field Figure 3-4. Data Processing Instructions 3-9 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3. 3-10 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result. Table 3-3. ARM Data Processing Instructions Assembler Mnemonic AND EOR WUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN OP Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Action Operand1 AND operand2 Operand1 EOR operand2 Operand1 - operand2 Operand2 operand1 Operand1 + operand2 Operand1 + operand2 + carry Operand1 - operand2 + carry - 1 Operand2 - operand1 + carry - 1 As AND, but result is not written As EOR, but result is not written As SUB, but result is not written As ADD, but result is not written Operand1 OR operand2 Operand2 (operand1 is ignored) Operand1 AND NOT operand2 (Bit clear) NOT operand2 (operand1 is ignored) The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed). 3-11 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-5. 11 7654 0 11 RS 87654 0 1 [6:5] Shift type 00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right [6:5] Shift type 00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right [11:7] Shift amount 5 bit unsigned integer [11:8] Shift register Shift amount specified in bottom-byte of Rs Figure 3-5. ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For example, the effect of LSL #5 is shown in Figure 3-6. 31 27 26 Contents of Rm 0 carry out Value of Operand 2 00000 Figure 3-6. Logical Shift Left NOTE LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7. 3-12 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET 31 Contents of Rm 54 0 carry out 00000 Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified. An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure 3-8. 31 30 Contents of Rm 54 0 carry out Value of Operand 2 Figure 3-8. Arithmetic Shift Right The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm. 3-13 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9. 31 Contents of Rm 54 0 carry out Value of Operand 2 Figure 3-9. Rotate Right The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10. 31 Contents of Rm 10 C in Value of Operand 2 carry out Figure 3-10. Rotate Right Extended 3-14 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET Register specified shift amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output. If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. If the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. LSL by 32 has result zero, carry out equal to bit 0 of Rm. 2. LSL by more than 32 has result zero, carry out zero. 3. LSR by 32 has result zero, carry out equal to bit 31 of Rm. 4. LSR by more than 32 has result zero, carry out zero. 5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm. 6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm. 7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction. 3-15 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2. WRITING TO R15 When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as described above. When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected. When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR. This allows state changes which atomically restore both PC and CPSR. This form of instruction should not be used in User mode. USING R15 AS AN OPERANDY If R15 (the PC) is used as an operand in a data processing instruction the register is used directly. The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead. TEQ, TST, CMP AND CMN OPCODES NOTE TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic. The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer operations should be used instead. The action of TEQP in the ARM7TDMI is to move SPSR_ NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively. 3-16 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX * * * MOV,MVN (single operand instructions). where: EXAMPLES ADDEQ TEQS R2,R4,R5 R4,#3 ; ; ; ; ; ; ; ; ; ; If the Z flag is set make R2:=R4+R5 Test R4 for equality with 3. (The S is in fact redundant as the assembler inserts it automatically.) Logical right shift R7 by the number in the bottom byte of R2, subtract result from R5, and put the answer into R4. Return from subroutine. Return from exception and restore CPSR from SPSR_mode. SUB R4,R5,R7,LSR R2 MOV MOVS PC,R14 PC,R14 3-17 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11. These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the CPSR or SPSR_ * * * * * In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the CPSR can be changed. In other (privileged) modes the entire CPSR can be changed. Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor will enter an unpredictable state. The SPSR register which is accessed depends on the mode at the time of execution. For example, only SPSR_fiq is accessible when the processor is in FIQ mode. You must not specify R15 as the source or destination register. Also, do not attempt to access an SPSR in User mode, since no such register exists. 3-18 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET MRS (transfer PSR contents to a register) 31 Cond 28 27 00010 23 22 21 Ps 001111 16 15 Rd 12 11 000000000000 0 [15:21] Destination Register [19:16] Source PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MRS (transfer register contents to PSR) 31 Cond 28 27 00010 23 22 21 Pd 101001111 12 11 00000000 43 Rm 0 [3:0] Source Register [22] Destination PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MRS (transfer register contents or immediate value to PSR flag bits only) 31 Cond 28 27 26 25 24 23 22 21 00 I 10 Pd 101001111 12 11 Source operand 0 [22] Destination PSR 0 = CPSR 1 = SPSR_ [25] Immediate Operand 0 = Source operand is a register 1 = SPSR_ [11:0] Source Operand 11 00000000 43 Rm 0 [3:0] Source Register [11:4] Source operand is an immediate value 11 Rotate 87 Imm 0 [7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm [31:28] Condition Field Figure 3-11. PSR Transfer 3-19 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM7TDMI (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM7TDMI programs and future processors, the following rules should be observed: * * The reserved bits should be preserved when changing the value in a PSR. Programs should not rely on specific values from the reserved bits when checking the PSR status, since they may read as one or zero in future processors. A read-modify-write strategy should therefore be used when altering the control bits of any PSR register; this involves transferring the appropriate PSR register to a general register using the MRS instruction, changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction. EXAMPLES The following sequence performs a mode change: MRS BIC ORR MSR R0,CPSR R0,R0,#0x1F R0,R0,#new_mode CPSR,R0 ; ; ; ; Take a copy of the CPSR. Clear the mode bits. Select new mode Write back the modified CPSR. When the aim is simply to change the condition code flags in a PSR, a value can be written directly to the flag bits without disturbing the control bits. The following instruction sets the N,Z,C and V flags: MSR CPSR_flg,#0xF0000000 ; Set all the flags regardless of their previous state ; (does not affect any control bits). No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits. INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles, where S is defined as Sequential (S-cycle). 3-20 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLY SYNTAX * * * MRS - transfer PSR contents to a register MRS{cond} Rd, The most significant four bits of the register contents are written to the N,Z,C & V flags respectively. * MSR - transfer immediate value to PSR flag bits only MSR{cond} The expression should symbolise a 32 bit value of which the most significant four bits are written to the N,Z,C and V flags respectively. Key: {cond} Rd and Rm EXAMPLES In User mode the instructions behave as follows: MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0xA0000000 Rd,CPSR ; ; ; ; CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0xA (set N,C; clear Z,V) Rd[31:0] <- CPSR[31:0] In privileged modes the instructions behave as follows: MSR MSR MSR MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0x50000000 SPSR_all,Rm SPSR_flg,Rm SPSR_flg,#0xC0000000 Rd,SPSR ; ; ; ; ; ; ; CPSR[31:0] <- Rm[31:0] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0x5 (set Z,V; clear N,C) SPSR_ 3-21 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication. 31 Cond 28 27 22 21 20 19 AS Rd 16 15 Rn 12 11 Rs 87 43 Rm 0 000000 1001 [15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code 0 = Do not after condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [31:28] Condition Field Figure 3-12. Multiply Instructions The multiply form of the instruction gives Rd:=Rm*Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd:=Rm*Rs+Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers. The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. For example consider the multiplication of the operands: Operand A Operand B Result 0xFFFFFFF6 0x0000001 0xFFFFFF38 3-22 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38. Operand Restrictions The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an operand or as the destination register. All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when required. 3-23 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected. INSTRUCTION CYCLE TIMES MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. m The number of 8 bit multiplier array cycles is required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows If bits [32:8] of the multiplier operand are all zero or all one. If bits [32:16] of the multiplier operand are all zero or all one. If bits [32:24] of the multiplier operand are all zero or all one. In all other cases. 1 2 3 4 ASSEMBLER SYNTAX MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} {S} Rd, Rm, Rs and Rn Two-character condition mnemonic. See Table 3-2.. Set condition codes if S present Expressions evaluating to a register number other than R15. EXAMPLES MUL MLAEQS R1,R2,R3 R1,R2,R3,R4 ; R1:=R2*R3 ; Conditionally R1:=R2*R3+R4, Setting condition codes. 3-24 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 Cond 28 27 23 22 21 20 19 UAS RdHi 16 15 RdLo 12 11 Rs 87 43 Rm 0 00001 1001 [11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers [20] Set Condition Code 0 = Do not alter condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [22] Unsigned 0 = Unsigned 1 = Signed [31:28] Condition Field Figure 3-13. Multiply Long Instructions The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs. The lower 32 bits of the 64 bit result are written to RdLo, the upper 32 bits of the result are written to RdHi. The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs + RdHi,RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi. The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. The SMULL and SMLAL instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result. 3-25 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR OPERAND RESTRICTIONS * * R15 must not be used as an operand or as a destination register. RdHi, RdLo, and Rm must all specify different registers. CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values. INSTRUCTION CYCLE TIMES MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows: For Signed INSTRUCTIONS SMULL, SMLAL: * * * * If bits [31:8] of the multiplier operand are all zero or all one. If bits [31:16] of the multiplier operand are all zero or all one. If bits [31:24] of the multiplier operand are all zero or all one. In all other cases. For Unsigned Instructions UMULL, UMLAL: * * * * If bits [31:8] of the multiplier operand are all zero. If bits [31:16] of the multiplier operand are all zero. If bits [31:24] of the multiplier operand are all zero. In all other cases. S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. 3-26 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic UMULL{cond}{S} RdLo,RdHi,Rm,Rs UMLAL{cond}{S} RdLo,RdHi,Rm,Rs SMULL{cond}{S} RdLo,RdHi,Rm,Rs SMLAL{cond}{S} RdLo,RdHi,Rm,Rs where: {cond} {S} RdLo, RdHi, Rm, Rs Two-character condition mnemonic. See Table 3-2. Set condition codes if S present Expressions evaluating to a register number other than R15. Description Unsigned Multiply Long Unsigned Multiply & Accumulate Long Signed Multiply Long Signed Multiply & Accumulate Long Purpose 32 x 32 = 64 32 x 32 + 64 = 64 32 x 32 = 64 32 x 32 + 64 = 64 EXAMPLES UMULL UMLALS R1,R4,R2,R3 R1,R5,R2,R3 ; R4,R1:=R2*R3 ; R5,R1:=R2*R3+R5,R1 also setting condition codes 3-27 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. 31 Cond 28 27 26 25 24 23 22 21 20 19 01 I PUBWL Rn 16 15 Rd 12 11 Offset 0 [15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Byte/Word Bit 0 = Transfer word quantity 1 = Transfer byte quantity [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset before transfer [25] Immediate Offset 0 = Offset is an immediate value [11:0] Offset 11 Immediate [11:0] Unsigned 12-bit immediate offset 11 Shift 43 Rm 0 0 [3:0] Offset register [11:4] Shift applied to Rm [31:28] Condition Field Figure 3-14. Single Data Transfer Instructions 3-28 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address. The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base value may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The only use of the W bit in a post-indexed data transfer is in privileged mode code, where setting the W bit forces nonprivileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section. However, the register specified shift amounts are not available in this instruction class. See Figure 3-5. BYTES AND WORDS This instruction class may be used to transfer a byte (B=1) or a word (B=0) between an ARM7TDMI register and memory. The action of LDR(B) and STR(B) instructions is influenced by the BIGEND control signal of ARM7TDMI core. The two possible configurations are described below. Little-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. Please see Figure 2-2. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) will normally use a word aligned address. However, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. This means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. Two shift operations are then required to clear or to sign extend the upper 16 bits. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31. 3-29 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR memory A A+3 B A+2 C A+1 D A 0 8 16 24 register A 24 B 16 C 8 D 0 LDR from word aligned address memory A A+3 B A+2 C A+1 D A 0 LDR from address offset by 2 8 D 0 16 C 8 24 B 16 register A 24 Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. Please see Figure 2-1. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31. 3-30 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the instruction plus 12. RESTRICTION ON THE USE OF BASE REGISTER When configured for late aborts, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. After an abort, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. EXAMPLE: LDR R0,[R1],R1 Therefore a post-indexed LDR or STR where Rm is the same register as Rn should not be used. DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STR instructions take 2N incremental cycles to execute. 3-31 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR ASSEMBLER SYNTAX Rd Rn and Rm can be: 1 An expression which generates an address: The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated. A pre-indexed addressing specification: [Rn] offset of zero [Rn,<#expression>]{!} offset of 2 3 {!} 3-32 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES STR STR LDR LDR LDREQB STR PLACE R1,[R2,R4]! R1,[R2],R4 R1,[R2,#16] R1,[R2,R3,LSL#2] R1,[R6,#5] R1,PLACE ; ; ; ; ; ; ; ; Store R1 at R2+R4 (both of which are registers) and write back address to R2. Store R1 at R2 and write back R2+R4 to R2. Load R1 from contents of R2+16, but don't write back. Load R1 from contents of R2+R3*4. Conditionally load byte at R6+5 into R1 bits 0 to 7, filling bits 8 to 31 with zeros. Generate PC relative offset to address PLACE. 3-33 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. 31 Cond 28 27 000 25 24 23 22 21 20 19 PU0WL Rn 16 15 Rd 12 11 0000 876543 1SH1 Rm 0 [3:0] Offset Register [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfword 1 = Signed byte 1 = Signed halfword [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field Figure 3-16. Halfword and Signed Data Transfer with Register Offset 3-34 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET 31 Cond 28 27 000 25 24 23 22 21 20 19 PU1WL Rn 16 15 Rd 12 11 Offset 876543 1SH1 Offset 0 [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfword 1 = Signed byte 1 = Signed halfword [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field Figure 3-17. Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing OFFSETS AND AUTO-INDEXING The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction, or a second register. The 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the MSB and bit 0 becomes the LSB. The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (postindexed, P=0) the base register is used as the transfer address. The W bit gives optional auto-increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The Write-back bit should not be set high (W=1) when post-indexed addressing is selected. 3-35 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM7TDMI register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below. SIGNED BYTE AND HALFWORD LOADS The S bit controls the loading of sign-extended data. When S=1 the H bit selects between Bytes (H=0) and Halfwords (H=1). The L bit should not be set low (Store) when Signed (S=1) operations have been selected. The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign bit. The LDRSH instruction loads the selected Half-word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15, the sign bit. The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the following section. ENDIANNESS AND BYTE/HALFWORD SELECTION Little-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-2. A halfword load (LDRSH or LDRH) expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary, (A[1]=1).The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword. A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour. 3-36 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-1. A halfword load (LDRSH or LDRH) expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary, (A[1]=1). The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword. A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour. USE OF R15 Write-back should not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 should not be specified as the register offset (Rm). When R15 is the source register (Rd) of a Half-word store (STRH) instruction, the stored address will be address of the instruction plus 12. DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from the main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Normal LDR(H,SH,SB) instructions take 1S + 1N + 1I. LDR(H,SH,SB) PC take 2S + 2N + 1I incremental cycles. S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STRH instructions take 2N incremental cycles to execute. 3-37 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR ASSEMBLER SYNTAX 2 3 4 {!} 3-38 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES LDRH ; ; ; R3,[R4,#14] ; R8,[R2],#-223 ; ; R11,[R0] ; ; ; R5, [PC,#(FRED-HERE-8)]; R1,[R2,-R3]! Load R1 from the contents of the halfword address contained in R2-R3 (both of which are registers) and write back address to R2 Store the halfword in R3 at R14+14 but don't write back. Load R8 with the sign extended contents of the byte address contained in R2 and write back R2-223 to R2. Conditionally load R11 with the sign extended contents of the halfword address contained in R0. Generate PC relative offset to address FRED. Store the halfword in R5 at address FRED STRH LDRSB LDRNESH HERE STRH FRED 3-39 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory. THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank (and non-user mode programs can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction, with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on. Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list should not be empty. Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12. 31 Cond 28 27 100 25 24 23 22 21 20 19 PUSWL Rn 16 15 Register list 0 [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] PSR & Force User Bit 0 = Do not load PSR or user mode 1 = Load PSR or force user mode [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer [31:28] Condition Field Figure 3-18. Block Data Transfer Instructions 3-40 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). Figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. 0x100C 0x100C Rn 0x1000 R1 0x1000 0x0FF4 1 0x100C R5 R1 Rn R7 R5 R1 2 0x0FF4 0x100C 0x1000 0x1000 0x0FF4 3 4 0x0FF4 Figure 3-19. Post-Increment Addressing 3-41 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR 0x100C R1 Rn 0x1000 0x100C 0x1000 0x0FF4 1 0x100C R5 R1 0x1000 Rn 2 R7 R5 R1 0x0FF4 0x100C 0x1000 0x0FF4 3 4 0x0FF4 Figure 3-20. Pre-Increment Addressing 0x100C 0x100C Rn 0x1000 R1 0x0FF4 1 0x100C 2 0x1000 0x0FF4 0x100C 0x1000 R5 R1 0x0FF4 3 Rn R7 R5 R1 4 0x1000 0x0FF4 Figure 3-21. Post-Decrement Addressing 3-42 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET 0x100C 0x100C Rn 0x1000 0x1000 0x0FF4 1 0x100C R1 2 0x0FF4 0x100C 0x1000 R5 R1 3 R7 R5 R1 4 0x1000 0x0FF4 Rn 0x0FF4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode. LDM with R15 in Transfer List and S Bit Set (Mode Changes) If the instruction is a LDM then SPSR_ 3-43 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value. A LDM will always overwrite the updated base if the base is in the list. DATA ABORTS Some legal addresses may be unacceptable to a memory management system, and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH. This can happen on any transfer during a multiple register load or store, and must be recoverable if ARM7TDMI is to be used in a virtual memory system. Abort during STM Instructions If the abort occurs during a store multiple instruction, ARM7TDMI takes little action until the instruction completes, whereupon it enters the data abort trap. The memory manager is responsible for preventing erroneous writes to the memory. The only change to the internal state of the processor will be the modification of the base register if write-back was specified, and this must be reversed by software (and the cause of the abort resolved) before the instruction may be retried. Aborts during LDM Instructions When ARM7TDMI detects a data abort during a load multiple instruction, it modifies the operation of the instruction to ensure that recovery is possible. * Overwriting of registers stops when the abort happens. The aborting load will not take place but earlier ones may have overwritten registers. The PC is always the last register to be written and so will always be preserved. The base register is restored, to its modified value if write-back was requested. This ensures recoverability in the case where the base register is also in the transfer list, and may have been overwritten before the abort occurred. * The data abort trap is taken when the load multiple has completed, and the system software must undo any base modification (and resolve the cause of the abort) before restarting the instruction. INSTRUCTION CYCLE TIMES Normal LDM instructions take nS + 1N + 1I and LDM PC takes (n+1)S + 2N + 1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STM instructions take (n-1)S + 2N incremental cycles to execute, where n is the number of words transferred. 3-44 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Addressing Mode Names There are different assembler mnemonics for each of the addressing modes, depending on whether the instruction is being used to support stacks or for other purposes. The equivalence between the names and the values of the bits in the instruction are shown in the following table 3-6. Table 3-6. Addressing Mode Names Name Pre-Increment Load Post-Increment Load Pre-Decrement Load Post-Decrement Load Pre-Increment Store Post-Increment Store Pre-Decrement Store Post-Decrement Store Stack LDMED LDMFD LDMEA LDMFA STMFA STMEA STMFD STMED Other LDMIB LDMIA LDMDB LDMDA STMIB STMIA STMDB STMDA L bit 1 1 1 1 0 0 0 0 P bit 1 0 1 0 1 0 1 0 U bit 1 1 0 0 1 1 0 0 FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required. The F and E refer to a "full" or "empty" stack, i.e. whether a pre-index has to be done (full) before storing to the stack. The A and D refer to whether the stack is ascending or descending. If ascending, a STM will go up and LDM down, if descending, vice-versa. IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean Increment After, Increment Before, Decrement After, Decrement Before. 3-45 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR EXAMPLES LDMFD STMIA LDMFD LDMFD STMFD SP!,{R0,R1,R2} R0,{R0-R15} SP!,{R15} SP!,{R15}^ R13,{R0-R14}^ ; ; ; ; ; ; ; Unstack 3 registers. Save all registers. R15 (SP), CPSR unchanged. R15 (SP), CPSR <- SPSR_mode (allowed only in privileged modes). Save user mode regs on stack (allowed only in privileged modes). These instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine: STMED BL LDMED SP!,{R0-R3,R14} somewhere SP!,{R0-R3,R15} ; ; ; ; Save R0 to R3 to use as workspace and R14 for returning. This nested call will overwrite R14 Restore workspace and return. 3-46 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP (SWP) 31 Cond 28 27 00010 23 22 21 20 19 B 00 Rn 16 15 Rd 12 11 0000 87 1001 43 Rm 0 [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-23. The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are "locked" together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable). This class of instruction is particularly useful for implementing software semaphores. The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old memory contents in the destination register (Rd). The same register may be specified as both the source and destination. The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together, and should be allowed to complete without interruption. This is important in multi-processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores; control of the memory must not be removed from a processor while it is performing a locked operation. BYTES AND WORDS This instruction class may be used to swap a byte (B=1) or a word (B=0) between an ARM7TDMI register and memory. The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers. In particular, the description of Big and Little Endian configuration applies to the SWP instruction. 3-47 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are defined as sequential (S-cycle), non-sequential, and internal (I-cycle), respectively. ASSEMBLER SYNTAX EXAMPLES SWP SWPB SWPEQ R0,R1,[R2] R2,R3,[R4] R0,R0,[R1] ; ; ; ; ; ; Load R0 with the word addressed by R2, and store R1 at R2. Load R2 with the byte addressed by R4, and store bits 0 to 7 of R3 at R4. Conditionally swap the contents of the word addressed by R1 with R0. 3-48 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below. 31 Cond 28 27 1111 24 23 Comment Field (Ignored by Processor) 0 [31:28] Condition Field Figure 3-24. Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed. RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR. Note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR. COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate information to the supervisor code. For instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions. INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are defined as sequential (S-cycle) and non-sequential (N-cycle). 3-49 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR ASSEMBLER SYNTAX SWI{cond} EXAMPLES SWI SWI SWINE Supervisor code The previous examples assume that suitable supervisor code exists, for instance: 0x08 B Supervisor EntryTable DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn *** ReadC WriteI+"k" 0 ; Get next character from read stream. ; Output a "k" to the write stream. ; Conditionally call supervisor with 0 in comment field. ; SWI entry point ; Addresses of supervisor routines ReadC WriteI Zero EQU 256 EQU 512 Supervisor STMFD LDR BIC MOV ADR LDR WriteIRtn *** EQU 0 R13,{R0-R2,R14} R0,[R14,#-4] R0,R0,#0xFF000000 R1,R0,LSR#8 R2,EntryTable R15,[R2,R1,LSL#2] ; ; ; ; ; ; ; ; ; SWI has routine required in bits 8-23 and data (if any) in bits 0-7. Assumes R13_svc points to a suitable stack Save work registers and return address. Get SWI instruction. Clear top 8 bits. Get routine offset. Get start address of entry table. Branch to appropriate routine. Enter with character in R0 bits 0-7. LDMFD R13,{R0-R2,R15}^ ; Restore workspace and return, ; restoring processor mode and flags. 3-50 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM7TDMI, and it will not wait for the operation to complete. The coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and ARM7TDMI to perform independent tasks in parallel. COPROCESSOR INSTRUCTIONS The S3C44B0X, unlike some other ARM-based processors, does not have an external coprocessor interface. It does not have a on-chip coprocessor also. So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C44B0X. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C44B0X, the coprocessor instructions are still described here in full for completeness. (Remember that any external coprocessor described in this section is a software emulation.) 31 Cond 28 27 1110 24 23 20 19 CRn 16 15 CRd 12 11 Cp# 87 Cp 543 0 CRm 0 CP Opc [3:0] Coprocessor operand register [7:5] Coprocessor information [11:8] Coprocessor number [15:12] Coprocessor destination register [19:16] Coprocessor operand register [23:20] Coprocessor operation code [31:28] Condition Field Figure 3-25. Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM7TDMI. The remaining bits are used by coprocessors. The above field names are used by convention, and particular coprocessors may redefine the use of all fields except CP# as appropriate. The CP# field is used to contain an identifying number (in the range 0 to 15) for each coprocessor, and a coprocessor will ignore any instruction which does not contain its number in the CP# field. The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field (and possibly in the CP field) on the contents of CRn and CRm, and place the result in CRd. 3-51 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). ASSEMBLER SYNTAX CDP{cond} p#, EXAMPLES CDP CDPEQ p1,10,c1,c2,c3 p2,5,c1,c2,c3,2 ; ; ; ; Request coproc 1 to do operation 10 on CR2 and CR3, and put the result in CR1. If Z flag is set request coproc 2 to do operation 5 (type 2) on CR2 and CR3, and put the result in CR1. 3-52 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory. ARM7TDMI is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred. 31 Cond 28 27 110 25 24 23 22 21 20 19 PUNWL Rn 16 15 CRd 12 11 CP# 87 Offset 0 [7:0] Unsigned 8 Bit Immediate Offset [11:8] Coprocessor Number [15:12] Coprocessor Source/Destination Register [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Transfer Length [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset before transfer [31:28] Condition Field Figure 3-26. Coprocessor Data Transfer Instructions THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register where more than one is to be transferred), and the N bit is used to choose one of two transfer length options. For instance N=0 could select the transfer of a single register, and N=1 could select the transfer of all the registers for context switching. 3-53 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR ADDRESSING MODES ARM7TDMI is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers. The 8 bit unsigned immediate offset is shifted left 2 bits and either added to (U=1) or subtracted from (U=0) the base register (Rn); this calculation may be performed either before (P=1) or after (P=0) the base is used as the transfer address. The modified base value may be overwritten back into the base register (if W=1), or the old value of the base may be preserved (W=0). Note that post-indexed addressing modes require explicit setting of the W bit, unlike LDR and STR which always write-back when post-indexed. The value of the base register, modified by the offset in a pre-indexed instruction, is used as the address for the transfer of the first word. The second word (if more than one is transferred) will go to or come from an address one word (4 bytes) higher than the first transfer, and the address will be incremented by one word for each subsequent transfer. ADDRESS ALIGNMENT The base address should normally be a word aligned quantity. The bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. USE OF R15 If Rn is R15, the value used will be the address of the instruction plus 8 bytes. Base write-back to R15 must not be specified. DATA ABORTS If the address is legal but the memory manager generates an abort, the data trap will be taken. The write-back of the modified base will take place, but all other processor state will be preserved. The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved, and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried. INSTRUCTION CYCLE TIMES Coprocessor data transfer instructions take (n-1)S + 2N + bI incremental cycles to execute, where: n b The number of words transferred. The number of cycles spent in the coprocessor busy-wait loop. S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. 3-54 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX 1 2 3 EXAMPLES LDC STCEQL p1,c2,table p2,c3,[R5,#24]! ; ; ; ; ; ; Load c2 of coproc 1 from address table, using a PC relative address. Conditionally store c3 of coproc 2 into an address 24 bytes up from R5, write this address back to R5, and use long transfer option (probably to store multiple words). NOTE Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will adjust the offset appropriately. 3-55 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM7TDMI and a coprocessor. An example of a coprocessor to ARM7TDMI register transfer (MRC) instruction would be a FIX of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to ARM7TDMI register. A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR). An important use of this instruction is to communicate control information directly from the coprocessor into the ARM7TDMI CPSR flags. As an example, the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution. 31 Cond 28 27 1110 24 23 21 20 19 CRn 16 15 Rd 12 11 CP# 87 CP 543 1 CRm 0 CP Opc L [3:0] Coprocessor Operand Register [7:5] Coprocessor Information [11:8] Coprocessor Number [15:12] ARM Source/Destination Register [19:16] Coprocessor Source/Destination Register [20] Load/Store Bit 0 = Store to coprocessor 1 = Load from coprocessor [21] Coprocessor Operation Mode [31:28] Condition Field Figure 3-27. Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. Other interpretations are allowed where the coprocessor functionality is incompatible with this one. The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform, CRn is the coprocessor register which is the source or destination of the transferred information, and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified. 3-56 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM7TDMI has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer. TRANSFERS FROM R15 A coprocessor register transfer from ARM7TDMI with R15 as the source register will store the PC+12. INSTRUCTION CYCLE TIMES MRC instructions take 1S + (b+1)I +1C incremental cycles to execute, where S, I and C are defined as sequential (S-cycle), internal (I-cycle), and coprocessor register transfer (C-cycle), respectively. MCR instructions take 1S + bI +1C incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. ASSEMBLER SYNTAX EXAMPLES MRC p2,5,R3,c5,c6 ; ; ; ; ; ; ; ; Request coproc 2 to perform operation 5 on c5 and c6, and transfer the (single 32-bit word) result back to R3. Request coproc 6 to perform operation 0 on R4 and place the result in c6. Conditionally request coproc 3 to perform operation 9 (type 2) on c5 and c6, and transfer the result back to R3. MCR MRCEQ p6,0,R4,c5,c6 p3,9,R3,c5,c6,2 3-57 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 31 Cond 28 27 011 25 24 xxxxxxxxxxxxxxxxxxxx 543 1 xxxx 0 Figure 3-28. Undefined Instruction If the condition is true, the undefined instruction trap will be taken. Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving CPA and CPB HIGH. INSTRUCTION CYCLE TIMES This instruction takes 2S + 1I + 1N cycles, where S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle). ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction. If it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. Until such time, this instruction must not be used. 3-58 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM7TDMI instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code. USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP BEQ CMP BEQ This can be replaced by CMP CMPNE BEQ Absolute Value TEQ RSBMI Rn,#0 Rn,Rn,#0 ; Test sign ; and 2's complement if necessary. Rn,#p Rm,#q Label ; If condition not satisfied try other test. Rn,#p Label Rm,#q Label ; If Rn=p OR Rm=q THEN GOTO Label. Multiplication by 4, 5 or 6 (Run Time) MOV CMP ADDCS ADDHI Rc,Ra,LSL#2 Rb,#5 Rc,Rc,Ra Rc,Rc,Ra ; ; ; ; Multiply by 4, Test value, Complete multiply by 5, Complete multiply by 6. Combining Discrete and Range Tests TEQ CMPNE MOVLS Rc,#127 Rc,# " "-1 Rc,# "" ; ; ; ; Discrete test, Range test IF Rc<= "" OR Rc=ASCII(127) THEN Rc:= "." 3-59 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows. MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Rcnt,#1 Rb,#0x80000000 Rb,Ra Rb,Rb,ASL#1 Rcnt,Rcnt,ASL#1 Div1 Rc,#0 Ra,Rb Ra,Ra,Rb Rc,Rc,Rcnt Rcnt,Rcnt,LSR#1 Rb,Rb,LSR#1 Div2 ; Enter with numbers in Ra and Rb. ; Bit to control the division. ; Move Rb until greater than Ra. Div1 Div2 ; ; ; ; ; ; Test for possible subtraction. Subtract if ok, Put relevant bit into result Shift control bit Halve unless finished. Divide result in Rc, remainder in Ra. Overflow Detection in the ARM7TDMI 1. Overflow in unsigned multiply with a 32-bit result UMULL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 3 to 6 cycles ; +1 cycle and a register 2. Overflow in signed multiply with a 32-bit result SMULL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd ASR#31 overflow ; 3 to 6 cycles ; +1 cycle and a register 3. Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 4 to 7 cycles ; +1 cycle and a register 4. Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd, ASR#31 overflow ; 4 to 7 cycles ; +1 cycle and a register 3-60 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL ADDS ADC BCS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers 6. Overflow in signed multiply accumulate with a 64 bit result SMULL ADDS ADC BVS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers NOTE Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. PSEUDO-RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. The basic algorithm is newbit:=bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). The entire operation can be done in 5 S cycles: ; ; ; ; ; ; ; Enter with seed in Ra (32 bits), Rb (1 bit in Rb lsb), uses Rc. Top bit into carry 33 bit rotate right Carry into lsb of Rb (involved!) (similarly involved!) new seed in Ra, Rb as before TST MOVS ADC EOR EOR Rb,Rb,LSR#1 Rc,Ra,RRX Rb,Rb,Rb Rc,Rc,Ra,LSL#12 Ra,Rc,Rc,LSR#20 MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2^n (1,2,4,8,16,32..) MOV Ra, Rb, LSL #n Multiplication by 2^n+1 (3,5,9,17..) ADD Ra,Ra,Ra,LSL #n Multiplication by 2^n-1 (3,7,15..) RSB Ra,Ra,Ra,LSL #n 3-61 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR Multiplication by 6 ADD MOV Ra,Ra,Ra,LSL #1 Ra,Ra,LSL#1 ; Multiply by 3 ; and then by 2 Multiply by 10 and add in extra number ADD ADD Ra,Ra,Ra,LSL#2 Ra,Rc,Ra,LSL#1 ; Multiply by 5 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1: D<>1: MOV MOV Rb,Ra,LSL #n {Rb := Ra*D} Rb,Rb,LSL #n 2. If C MOD 4 = 1, say C = 2^n*D+1, D odd, n>1: D=1: D<>1: ADD ADD Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n 3. If C MOD 4 = 3, say C = 2^n*D-1, D odd, n>1: D=1: D<>1: RSB RSB Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n This is not quite optimal, but close. An example of its non-optimality is multiply by 45 which is done by: RSB RSB ADD rather than by: ADD ADD Rb,Ra,Ra,LSL#3 Rb,Rb,Rb,LSL#2 ; Multiply by 9 ; Multiply by 5*9 = 45 Rb,Ra,Ra,LSL#2 Rb,Ra,Rb,LSL#2 Rb,Ra,Rb,LSL# 2 ; Multiply by 3 ; Multiply by 4*3-1 = 11 ; Multiply by 4*11+1 = 45 3-62 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; ; ; ; ; ; ; ; ; Enter with address in Ra (32 bits) uses Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Get word aligned address Get 64 bits containing answer Correction factor in bytes ...now in bits and test if aligned Produce bottom of result word (if not aligned) Get other shift amount Combine two halves to get result BIC LDMIA AND MOVS MOVNE RSBNE ORRNE Rb,Ra,#3 Rb,{Rd,Rc} Rb,Ra,#3 Rb,Rb,LSL#3 Rd,Rd,LSR Rb Rb,Rb,#32 Rd,Rd,Rc,LSL Rb 3-63 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR NOTES 3-64 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM7TDMI core. As the Thumb instructions are compressed ARM instructions, the Thumb instructions have the 16-bit format instructions and have some restrictions. The restrictions by 16-bit format is fully notified for using the Thumb instructions. FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 B 0 1 0 1 1 0 1 1 0 1 1 0 H 9 8 7 6 1 Op 0 0 1 L H L L L SP 0 L L 0 1 B S 0 1 Op Rd 0 1 Ro Ro Offset5 Offset5 Rd Rd 0 0 Rb Cond 1 1 1 0 R S Op 1 I 9 8 Offset5 Op Rd Op H1 H2 Rn/offset3 7 6 5 4 Rs Rs Offset8 Rs Rs/Hs Word8 Rb Rb Rb Rb Word8 Word8 SWord7 Rlist Rlist Softset8 Value8 Offset11 Offset 5 4 3 2 1 0 Rd Rd Rd Rd Rd Rd/Hd 3 2 1 Rd Rd 0 Move Shifted register Add/subtract Move/compare/add/ subtract immediate ALU operations Hi register operations /branch exchange PC-relative load Load/store with register offset Load/store sign-extended byte/halfword Load/store with immediate offset Load/store halfword SP-relative load/store Load address Add offset to stack pointer Push/pop register Multiple load/store Conditional branch Software interrupt Unconditional branch Long branch with link 15 14 13 12 11 10 Figure 3-29. THUMB Instruction Set Formats 3-65 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 3-7. THUMB Instruction Set Opcodes Mnemonic ADC ADD AND ASR B Bxx BIC BL BX CMN CMP EOR LDMIA LDR LDRB LDRH LSL LDSB LDSH LSR MOV MUL MVN Instruction Add with Carry Add AND Arithmetic Shift Right Unconditional branch Conditional branch Bit Clear Branch and Link Branch and Exchange Compare Negative Compare EOR Load multiple Load word Load byte Load halfword Logical Shift Left Load sign-extended byte Load sign-extended halfword Logical Shift Right Move register Multiply Move Negative register Lo-Register Operand Y Y Y Y Y Y Y - Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Hi-Register Operand - - - - - - - - Y - Y - - - - - - - - - Y - - Condition Codes Set Y Y (1) Y Y - - Y - - Y Y Y - - - - Y - - Y Y (2) Y Y 3-66 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3-7. THUMB Instruction Set Opcodes (Continued) Mnemonic NEG ORR POP PUSH ROR SBC STMIA STR STRB STRH SWI SUB TST Negate OR Pop register Push register Rotate Right Subtract with Carry Store Multiple Store word Store byte Store halfword Software Interrupt Subtract Test bits Instruction Lo-Register Operand Y Y Y Y Y Y Y Y Y Y - Y Y Hi-Register Operand - - - - - - - - - - - - - Condition Codes Set Y Y - - Y Y - - - - - Y Y NOTES: 1. The condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. The condition codes are unaffected by the format 5 version of this instruction. 3-67 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 1: MOVE SHIFTED REGISTER 15 0 14 0 13 0 12 Op 11 10 Offset5 6 5 Rs 3 2 Rd 0 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 3-30. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 3-8. NOTE All instructions in this group set the CPSR condition codes. Table 3-8. Summary of Format 1 Instructions OP 00 01 THUMB Assembler LSL Rd, Rs, #Offset5 LSR Rd, Rs, #Offset5 ARM Equipment Action MOVS Rd, Rs, LSL #Offset5 Shift Rs left by a 5-bit immediate value and store the result in Rd. MOVS Rd, Rs, LSR #Offset5 Perform logical shift right on Rs by a 5-bit immediate value and store the result in Rd. MOVS Rd, Rs, ASR #Offset5 Perform arithmetic shift right on Rs by a 5-bit immediate value and store the result in Rd. 10 ASR Rd, Rs, #Offset5 3-68 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-8. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 ; Logical shift right the contents ; of R5 by 27 and store the result in R2. ; Set condition codes on the result. 3-69 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 2: ADD/SUBTRACT 15 0 14 0 13 0 12 1 11 1 10 1 9 Op 8 Rn/Offset3 6 5 Rs 3 2 Rd 0 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 3-31. Format 2 OPERATION These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register. The THUMB assembler syntax is shown in Table 3-9. NOTE All instructions in this group set the CPSR condition codes. Table 3-9. Summary of Format 2 Instructions OP 0 0 1 1 I 0 1 0 1 THUMB Assembler ADD Rd, Rs, Rn ADD Rd, Rs, #Offset3 SUB Rd, Rs, Rn SUB Rd, Rs, #Offset3 ARM Equipment ADDS Rd, Rs, Rn Action Add contents of Rn to contents of Rs. Place result in Rd. ADDS Rd, Rs, #Offset3 Add 3-bit immediate value to contents of Rs. Place result in Rd. SUBS Rd, Rs, Rn Subtract contents of Rn from contents of Rs. Place result in Rd. SUBS Rd, Rs, #Offset3 Subtract 3-bit immediate value from contents of Rs. Place result in Rd. 3-70 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SUB R0, R3, R4 R6, R2, #6 ; R0 := R3 + R4 and set condition codes on the result. ; R6 := R2 - 6 and set condition codes. 3-71 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 0 14 0 13 0 12 Op 11 10 Rd 8 7 Offset8 0 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 3-32. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 3-10. NOTE All instructions in this group set the CPSR condition codes. Table 3-10. Summary of Format 3 Instructions OP 00 01 10 11 THUMB Assembler MOV Rd, #Offset8 CMP Rd, #Offset8 ADD Rd, #Offset8 SUB Rd, #Offset8 ARM Equipment MOVS Rd, #Offset8 CMP Rd, #Offset8 ADDS Rd, Rd, #Offset8 SUBS Rd, Rd, #Offset8 Action Move 8-bit immediate value into Rd. Compare contents of Rd with 8-bit immediate value. Add 8-bit immediate value to contents of Rd and place the result in Rd. Subtract 8-bit immediate value from contents of Rd and place the result in Rd. 3-72 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-10. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES MOV CMP ADD SUB R0, #128 R2, #62 R1, #255 R6, #145 ; ; ; ; R0 := 128 and set condition codes Set condition codes on R2 - 62 R1 := R1 + 255 and set condition codes R6 := R6 - 145 and set condition codes 3-73 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 4: ALU OPERATIONS 15 0 14 0 13 0 12 0 11 0 10 0 9 Op 6 5 Rs 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 3-33. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes. Table 3-11. Summary of Format 4 Instructions OP 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 THUMB Assembler AND Rd, Rs EOR Rd, Rs LSL Rd, Rs LSR Rd, Rs ASR Rd, Rs ADC Rd, Rs SBC Rd, Rs ROR Rd, Rs TST Rd, Rs NEG Rd, Rs CMP Rd, Rs CMN Rd, Rs ORR Rd, Rs MUL Rd, Rs BIC Rd, Rs MVN Rd, Rs ARM Equipment ANDS Rd, Rd, Rs EORS Rd, Rd, Rs MOVS Rd, Rd, LSL Rs MOVS Rd, Rd, LSR Rs MOVS Rd, Rd, ASR Rs ADCS Rd, Rd, Rs SBCS Rd, Rd, Rs MOVS Rd, Rd, ROR Rs TST Rd, Rs RSBS Rd, Rs, #0 CMP Rd, Rs CMN Rd, Rs ORRS Rd, Rd, Rs MULS Rd, Rs, Rd BICS Rd, Rd, Rs MVNS Rd, Rs Action Rd:= Rd AND Rs Rd:= Rd EOR Rs Rd := Rd << Rs Rd := Rd >> Rs Rd := Rd ASR Rs Rd := Rd + Rs + C-bit Rd := Rd - Rs - NOT C-bit Rd := Rd ROR Rs Set condition codes on Rd AND Rs Rd = - Rs Set condition codes on Rd - Rs Set condition codes on Rd + Rs Rd := Rd OR Rs Rd := Rs * Rd Rd := Rd AND NOT Rs Rd := NOT Rs 3-74 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES EOR ROR NEG CMP MUL R3, R4 R1, R0 R5, R3 R2, R6 R0, R7 ; ; ; ; ; ; ; R3 := R3 EOR R4 and set condition codes Rotate Right R1 by the value in R0, store the result in R1 and set condition codes Subtract the contents of R3 from zero, Store the result in R5. Set condition codes ie R5 = - R3 Set the condition codes on the result of R2 - R6 R0 := R7 * R0 and set condition codes 3-75 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 0 14 0 13 0 12 0 11 0 10 0 9 Op 8 7 H1 6 H2 5 Rs/Hs 3 2 Rd/Hd 0 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 3-34. Format 5 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers. The fourth, BX, allows a Branch to be performed which may also be used to switch processor state. The THUMB assembler syntax is shown in Table 3-12. NOTE In this group only CMP (Op = 01) sets the CPSR condition codes. The action of H1= 0, H2 = 0 for Op = 00 (ADD), Op =01 (CMP) and Op = 10 (MOV) is undefined, and should not be used. Table 3-12. Summary of Format 5 Instructions Op 00 00 00 01 H1 0 1 1 0 H2 1 0 1 1 THUMB assembler ADD Rd, Hs ADD Hd, Rs ADD Hd, Hs CMP Rd, Hs ARM equivalent ADD Rd, Rd, Hs ADD Hd, Hd, Rs ADD Hd, Hd, Hs CMP Rd, Hs Action Add a register in the range 8-15 to a register in the range 0-7. Add a register in the range 0-7 to a register in the range 8-15. Add two registers in the range 8-15 Compare a register in the range 0-7 with a register in the range 8-15. Set the condition code flags on the result. Compare a register in the range 8-15 with a register in the range 0-7. Set the condition code flags on the result. 01 1 0 CMP Hd, Rs CMP Hd, Rs 3-76 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3-12. Summary of Format 5 Instructions (Continued) Op 01 H1 1 H2 1 THUMB assembler CMP Hd, Hs ARM equivalent CMP Hd, Hs Action Compare two registers in the range 8-15. Set the condition code flags on the result. Move a value from a register in the range 8-15 to a register in the range 07. Move a value from a register in the range 0-7 to a register in the range 8-15. Move a value between two registers in the range 8-15. Perform branch (plus optional state change) to address in a register in the range 0-7. Perform branch (plus optional state change) to address in a register in the range 8-15. 10 0 1 MOV Rd, Hs MOV Rd, Hs 10 1 0 MOV Hd, Rs MOV Hd, Rs 10 11 1 0 1 0 MOV Hd, Hs BX Rs MOV Hd, Hs BX Rs 11 0 1 BX Hs BX Hs INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register. Bit 0 of the address determines the processor state on entry to the routine: Bit 0 = 0 Bit 0 = 1 Causes the processor to enter ARM state. Causes the processor to enter THUMB state. NOTE The action of H1 = 1 for this instruction is undefined, and should not be used. 3-77 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR EXAMPLES Hi-Register Operations ADD CMP MOV PC, R5 R4, R12 R15, R14 ; ; ; ; ; PC := PC + R5 but don't set the condition codes. Set the condition codes on the result of R4 - R12. Move R14 (LR) into R15 (PC) but don't set the condition codes, eg. return from subroutine. Branch and Exchange ADR MOV BX R1,outofTHUMB R11,R1 R11 ; Switch from THUMB to ARM state. ; Load address of outofTHUMB into R1. ; Transfer the contents of R11 into the PC. ; Bit 0 of R11 determines whether ; ARM or THUMB state is entered, ie. ARM state here. * * ALIGN CODE32 outofTHUMB ; Now processing ARM instructions... USING R15 AS AN OPERAND If R15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. Executing a BX PC in THUMB state from a non-word aligned address will result in unpredictable execution. 3-78 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 6: PC-RELATIVE LOAD 15 0 14 0 13 0 12 0 11 0 10 Rd 8 7 Word 8 0 [7:0] Immediate Value [10:8] Destination Register Figure 3-35. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below. Table 3-13. Summary of PC-Relative Load Instruction THUMB assembler LDR Rd, [PC, #Imm] ARM equivalent LDR Rd, [R15, #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the PC. Load the word from the resulting address into Rd. NOTE: The value specified by #Imm is a full 10-bit address, but must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in field Word 8. The value of the PC will be 4 bytes greater than the address of this instruction, but bit 1 of the PC is forced to 0 to ensure it is word aligned. 3-79 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; ; ; ; ; Load into R3 the word found at the address formed by adding 844 to PC. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 211 as the Word8 value. 3-80 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 7: LOAD/STORE WITH REGISTER OFFSET 15 0 14 1 13 0 12 1 11 L 10 B 9 0 8 Ro 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-36. Format 7 3-81 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are preindexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 3-14. Table 3-14. Summary of Format 7 Instructions L 0 B 0 THUMB assembler STR Rd, [Rb, Ro] ARM equivalent STR Rd, [Rb, Ro] Action Pre-indexed word store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the contents of Rd at the address. Pre-indexed byte store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the byte value in Rd at the resulting address. Pre-indexed word load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the contents of the address into Rd. Pre-indexed byte load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the byte value at the resulting address. 0 1 STRB Rd, [Rb, Ro] STRB Rd, [Rb, Ro] 1 0 LDR Rd, [Rb, Ro] LDR Rd, [Rb, Ro] 1 1 LDRB Rd, [Rb, Ro] LDRB Rd, [Rb, Ro] INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-14. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR LDRB R3, [R2,R6] R2, [R0,R7] ; ; ; ; Store word in R3 at the address formed by adding R6 to R2. Load into R2 the byte found at the address formed by adding R7 to R0. 3-82 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD 15 0 14 1 13 0 12 1 11 H 10 S 9 1 8 Ro 6 5 Rb 3 2 Rd 0 [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 3-37. Format 8 OPERATION These instructions load optionally sign-extended bytes or halfwords, and store halfwords. The THUMB assembler syntax is shown below. Table 3-15. Summary of format 8 instructions L 0 B 0 THUMB assembler STRH Rd, [Rb, Ro] ARM equivalent STRH Rd, [Rb, Ro] Store halfword: Add Ro to base address in Rb. Store bits 0-15 of Rd at the resulting address. 0 1 LDRH Rd, [Rb, Ro] LDRH Rd, [Rb, Ro] Load halfword: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to 0. 1 0 LDSB Rd, [Rb, Ro] LDRSB Rd, [Rb, Ro] Load sign-extended byte: Add Ro to base address in Rb. Load bits 0-7 of Rd from the resulting address, and set bits 8-31 of Rd to bit 7. 1 1 LDSH Rd, [Rb, Ro] LDRSH Rd, [Rb, Ro] Load sign-extended halfword: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to bit 15. Action 3-83 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH LDSB LDSH R4, [R3, R0] R2, [R7, R1] R3, [R4, R2] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding R0 to R3. Load into R2 the sign extended byte found at the address formed by adding R1 to R7. Load into R3 the sign extended halfword found at the address formed by adding R2 to R4. 3-84 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET 15 0 14 1 13 1 12 B 11 L 10 Offset5 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 3-38. Format 9 3-85 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 3-16. Table 3-16. Summary of Format 9 Instructions L 0 B 0 THUMB assembler STR Rd, [Rb, #Imm] ARM equivalent STR Rd, [Rb, #Imm] Action Calculate the target address by adding together the value in Rb and Imm. Store the contents of Rd at the address. Calculate the source address by adding together the value in Rb and Imm. Load Rd from the address. Calculate the target address by adding together the value in Rb and Imm. Store the byte value in Rd at the address. Calculate source address by adding together the value in Rb and Imm. Load the byte value at the address into Rd. 1 0 LDR Rd, [Rb, #Imm] LDR Rd, [Rb, #Imm] 0 1 STRB Rd, [Rb, #Imm] STRB Rd, [Rb, #Imm] 1 1 LDRB Rd, [Rb, #Imm] LDRB Rd, [Rb, #Imm] NOTE: For word accesses (B = 0), the value specified by #Imm is a full 7-bit address, but must be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Offset5 field. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-16. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R2, [R5,#116] ; ; ; ; ; ; ; ; Load into R2 the word found at the address formed by adding 116 to R5. Note that the THUMB opcode will contain 29 as the Offset5 value. Store the lower 8 bits of R1 at the address formed by adding 13 to R0. Note that the THUMB opcode will contain 13 as the Offset5 value. STRB R1, [R0,#13] 3-86 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 10: LOAD/STORE HALFWORD 15 0 14 1 13 0 12 0 11 L 10 Offset5 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-39. Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value. The THUMB assembler syntax is shown in Table 3-17. Table 3-17. Halfword Data Transfer Instructions L 0 1 THUMB assembler STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] ARM equivalent STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] Action Add #Imm to base address in Rb and store bits 0 - 15 of Rd at the resulting address. Add #Imm to base address in Rb. Load bits 0-15 from the resulting address into Rd and set bits 16-31 to zero. NOTE: #Imm is a full 6-bit address but must be halfword-aligned (ie with bit 0 set to 0) since the assembler places #Imm >> 1 in the Offset5 field. 3-87 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-17. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding 56 R1. Note that the THUMB opcode will contain 28 as the Offset5 value. Load into R4 the halfword found at the address formed by adding 4 to R7. Note that the THUMB opcode will contain 2 as the Offset5 value. LDRH R4, [R7, #4] 3-88 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 11: SP-RELATIVE LOAD/STORE 15 1 14 0 13 0 12 1 11 L 10 Rd 8 7 Word 8 0 [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-40. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table. Table 3-18. SP-Relative Load/Store Instructions L 0 THUMB assembler STR Rd, [SP, #Imm] ARM equivalent STR Rd, [R13 #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Store the contents of Rd at the resulting address. Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Load the word from the resulting address into Rd. 1 LDR Rd, [SP, #Imm] LDR Rd, [R13 #Imm] NOTE: The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Word8 field. 3-89 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-18. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR R4, [SP,#492] ; ; ; ; Store the contents of R4 at the address formed by adding 492 to SP (R13). Note that the THUMB opcode will contain 123 as the Word8 value. 3-90 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 12: LOAD ADDRESS 15 1 14 0 13 1 12 0 11 SP 10 Rd 8 7 Word 8 0 [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 3-41. Format 12 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address into a register. The THUMB assembler syntax is shown in the following table. Table 3-19. Load Address L 0 THUMB assembler ADD Rd, PC, #Imm ARM equivalent ADD Rd, R15, #Imm Action Add #Imm to the current value of the program counter (PC) and load the result into Rd. Add #Imm to the current value of the stack pointer (SP) and load the result into Rd. 1 ADD Rd, SP, #Imm ADD Rd, R13, #Imm NOTE: The value specified by #Imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #Imm >> 2 in field Word 8. Where the PC is used as the source register (SP = 0), bit 1 of the PC is always read as 0. The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. The CPSR condition codes are unaffected by these instructions. 3-91 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-19. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R2, PC, #572 ; ; ; ; ; ; ; ; R2 := PC + 572, but don't set the condition codes. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 143 as the Word8 value. R6 := SP (R13) + 212, but don't set the condition codes. Note that the THUMB opcode will contain 53 as the Word 8 value. ADD R6, SP, #212 3-92 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 13: ADD OFFSET TO STACK POINTER 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 S 6 SWord 7 0 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 3-42. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax. Table 3-20. The ADD SP Instruction L 0 1 THUMB assembler ADD SP, #Imm ADD SP, # -Imm ARM equivalent ADD R13, R13, #Imm SUB R13, R13, #Imm Action Add #Imm to the stack pointer (SP). Add #-Imm to the stack pointer (SP). NOTE: The offset specified by #Imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #Imm to an 8-bit sign + magnitude number before placing it in field SWord7. The condition codes are not set by this instruction. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-20. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SP, #268 ; ; ; ; ; ; SP (R13) := SP + 268, but don't set the condition codes. Note that the THUMB opcode will contain 67 as the Word7 value and S=0. SP (R13) := SP - 104, but don't set the condition codes. Note that the THUMB opcode will contain 26 as the Word7 value and S=1. ADD SP, #-104 3-93 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 14: PUSH/POP REGISTERS 15 1 14 0 13 1 12 1 11 L 10 1 9 0 8 R 7 Rlist 0 [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-43. Format 14 OPERATION The instructions in this group allow registers 0-7 and optionally LR to be pushed onto the stack, and registers 0-7 and optionally PC to be popped off the stack. The THUMB assembler syntax is shown in Table 3-21. NOTE The stack is always assumed to be Full Descending. Table 3-21. PUSH and POP Instructions L 0 0 B 0 1 THUMB assembler PUSH { Rlist } PUSH { Rlist, LR } ARM equivalent STMDB R13!, { Rlist } STMDB R13!, { Rlist, R14 } LDMIA R13!, { Rlist } Action Push the registers specified by Rlist onto the stack. Update the stack pointer. Push the Link Register and the registers specified by Rlist (if any) onto the stack. Update the stack pointer. Pop values off the stack into the registers specified by Rlist. Update the stack pointer. 1 0 POP { Rlist } 1 1 POP { Rlist, PC } LDMIA R13!, {Rlist, R15} Pop values off the stack and load into the registers specified by Rlist. Pop the PC off the stack. Update the stack pointer. 3-94 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-21. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES PUSH {R0-R4,LR} ; ; ; ; ; ; ; Store R0,R1,R2,R3,R4 and R14 (LR) at the stack pointed to by R13 (SP) and update R13. Useful at start of a sub-routine to save workspace and return address. Load R2,R6 and R15 (PC) from the stack pointed to by R13 (SP) and update R13. Useful to restore workspace and return from sub-routine. POP {R2,R6,PC} 3-95 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 15: MULTIPLE LOAD/STORE 15 1 14 1 13 0 12 0 11 L 10 Rb 8 7 Rlist 0 [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-44. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table. Table 3-22. The Multiple Load/Store Instructions L 0 THUMB assembler STMIA Rb!, { Rlist } ARM equivalent STMIA Rb!, { Rlist } Action Store the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. Load the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. 1 LDMIA Rb!, { Rlist } LDMIA Rb!, { Rlist } INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-22. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STMIA R0!, {R3-R7} ; ; ; ; Store the contents of registers R3-R7 starting at the address specified in R0, incrementing the addresses for each word. Write back the updated value of R0. 3-96 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 16: CONDITIONAL BRANCH 15 1 14 1 13 0 12 1 11 Cond 8 7 SOffset 8 0 [7:0] 8-bit Signed Immediate [11:8] Condition Figure 3-45. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. The THUMB assembler syntax is shown in the following table. Table 2-23. The Conditional Branch Instructions L 0000 0001 0010 0011 0100 0101 0110 0111 1000 THUMB assembler BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label ARM equivalent BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label Action Branch if Z set (equal) Branch if Z clear (not equal) Branch if C set (unsigned higher or same) Branch if C clear (unsigned lower) Branch if N set (negative) Branch if N clear (positive or zero) Branch if V set (overflow) Branch if V clear (no overflow) Branch if C set and Z clear (unsigned higher) 3-97 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR Table 2-23. The Conditional Branch Instructions (Continued) L 1001 1010 1011 1100 1101 THUMB assembler BLS label BGE label BLT label BGT label BLE label ARM equivalent BLS label BGE label BLT label BGT label BLE label Action Branch if C clear or Z set (unsigned lower or same) Branch if N set and V set, or N clear and V clear (greater or equal) Branch if N set and V clear, or N clear and V set (less than) Branch if Z clear, and either N set and V set or N clear and V clear (greater than) Branch if Z set, or N set and V clear, or N clear and V set (less than or equal) NOTES 1. While label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0) since the assembler actually places label >> 1 in field SOffset8. 2. Cond = 1110 is undefined, and should not be used. Cond = 1111 creates the SWI instruction: see . INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-23. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES CMP R0, #45 BGT over * * * ; Branch to over-if R0 > 45. ; Note that the THUMB opcode will contain ; the number of halfwords to offset. ; Must be halfword aligned. over 3-98 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 17: SOFTWARE INTERRUPT 15 1 14 1 13 0 12 1 11 1 10 1 9 1 8 1 7 Value 8 0 [7:0] Comment Field Figure 3-46. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instruction is shown below. Table 3-24. The SWI Instruction THUMB assembler SWI Value 8 ARM equivalent SWI Value 8 Action Perform Software Interrupt: Move the address of the next instruction into LR, move CPSR to SPSR, load the SWI vector address (0x8) into the PC. Switch to ARM state and enter SVC mode. NOTE: Value8 is used solely by the SWI handler; it is ignored by the processor. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-24. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES SWI 18 ; Take the software interrupt exception. ; Enter Supervisor mode with 18 as the ; requested SWI number. 3-99 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 18: UNCONDITIONAL BRANCH 15 1 14 1 13 1 12 0 11 0 10 Offset11 0 [10:0] Immediate Value Figure 3-47. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. Table 3-25. Summary of Branch Instruction THUMB assembler B label ARM equivalent BAL label (halfword offset) Action Branch PC relative +/- Offset11 << 1, where label is PC +/- 2048 bytes. NOTE: The address specified by label is a full 12-bit two's complement address, but must always be halfword aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the Offset11 field. EXAMPLES here B here B jimmy * * * ; ; ; ; Branch onto itself. Assembles to 0xE7FE. (Note effect of PC offset). Branch to 'jimmy'. Note that the THUMB opcode will contain the number of jimmy * ; halfwords to offset. ; Must be halfword aligned. 3-100 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 19: LONG BRANCH WITH LINK 15 1 14 1 13 1 12 1 11 H 10 Offset 0 [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 3-48. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two THUMB instructions. Instruction 1 (H = 0) In the first instruction the Offset field contains the upper 11 bits of the target address. This is shifted left by 12 bits and added to the current PC address. The resulting address is placed in LR. Instruction 2 (H =1) In the second instruction the Offset field contains an 11-bit representation lower half of the target address. This is shifted left by 1 bit and added to LR. LR, which now contains the full 23-bit address, is placed in PC, the address of the instruction following the BL is placed in LR and bit 0 of LR is set. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction 3-101 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 3-26. The BL Instruction L 0 1 THUMB assembler BL label none ARM equivalent Action LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow << 1 LR := temp | 1 EXAMPLES BL faraway next * * faraway * * ; ; ; ; ; ; ; Unconditionally Branch to 'faraway' and place following instruction address, ie "next", in R14,the Link register and set bit 0 of LR high. Note that the THUMB opcodes will contain the number of halfwords to offset. Must be Half-word aligned. 3-102 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents. For other constants it is generally better to use the built-in MUL instruction rather than using a sequence of 4 or more instructions. Thumb ARM 1. Multiplication by 2^n (1,2,4,8,...) LSL Ra, Rb, LSL #n ; MOV Ra, Rb, LSL #n 2. Multiplication by 2^n+1 (3,5,9,17,...) LSL ADD Rt, Rb, #n Ra, Rt, Rb ; ADD Ra, Rb, Rb, LSL #n 3. Multiplication by 2^n-1 (3,7,15,...) LSL SUB Rt, Rb, #n Ra, Rt, Rb ; RSB Ra, Rb, Rb, LSL #n 4. Multiplication by -2^n (-2, -4, -8, ...) LSL MVN Ra, Rb, #n Ra, Ra ; MOV Ra, Rb, LSL #n ; RSB Ra, Ra, #0 5. Multiplication by -2^n-1 (-3, -7, -15, ...) LSL SUB Rt, Rb, #n Ra, Rb, Rt ; SUB Ra, Rb, Rb, LSL #n Multiplication by any C = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n Effectively this is any of the multiplications in 2 to 5 followed by a final shift. This allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) LSL Ra, Ra, #n ; (2..5) ; MOV Ra, Ra, LSL #n 3-103 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ; remainder in R1 ;Get abs value of R0 into R3 ASR R2, R0, #31 EOR R0, R2 SUB R3, R0, R2 ; Get 0 or -1 in R2 depending on sign of R0 ; EOR with -1 (0xFFFFFFFF) if negative ; and ADD 1 (SUB -1) to get abs value ;SUB always sets flag so go & report division by 0 if necessary BEQ divide_by_zero ;Get abs value of R1 by xoring with 0xFFFFFFFF and adding 1 if negative ASR R0, R1, #31 ; Get 0 or -1 in R3 depending on sign of R1 EOR R1, R0 ; EOR with -1 (0xFFFFFFFF) if negative SUB R1, R0 ; and ADD 1 (SUB -1) to get abs value ;Save signs (0 or -1 in R0 & R2) for later use in determining ; sign of quotient & remainder. PUSH {R0, R2} ;Justification, shift 1 bit at a time until divisor (R0 value) ; is just <= than dividend (R1 value). To do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. LSR R0, R1, #1 MOV R2, R3 B %FT0 just_l LSL R2, #1 0 CMP R2, R0 BLS just_l MOV R0, #0 ; Set accumulator to 0 B %FT0 ; Branch into division loop div_l 0 LSR CMP BCC SUB ADC CMP BNE R2, #1 R1, R2 %FT0 R1, R2 R0, R0 R2, R3 div_l ; Test subtract ; If successful do a real subtract ; Shift result and add 1 if subtract succeeded ; Terminate when R2 == R3 (ie we have just ; tested subtracting the 'ones' value). 0 3-104 S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result sign = - 1 SUB R0, R3 EOR R1, R2 ; Negate remainder if dividend sign = - 1 SUB R1, R2 MOV pc, lr ARM Code signed_divide ANDS RSBMI EORS ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 RSBCS ; Effectively zero a4 as top bit will be shifted out later a4, a1, #&80000000 a1, a1, #0 ip, a4, a2, ASR #32 a2, a2, #0 ;Central part is identical code to udiv (without MOV a4, #0 which comes for free as part of signed entry sequence) MOVS a3, a1 BEQ divide_by_zero just_l CMP MOVLS BLO div_l CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV a2, a3 a4, a4, a4 a2, a2, a3 a3, a1 a3, a3, LSR #1 s_loop2 a1, a4 ip, ip, ASL #1 a1, a1, #0 a2, a2, #0 pc, lr a3, a2, LSR #1 a3, a3, LSL #1 s_loop ; Justification stage shifts 1 bit at a time ; NB: LSL #1 is always OK if LS succeeds 3-105 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 MOV LSR SUB LSR ADD LSR ADD LSR ADD LSR ASL ADD ASL SUB CMP BLT ADD SUB 0 MOV ARM Code udiv10 SUB SUB ADD ADD ADD MOV ADD SUBS ADDPL ADDMI MOV a2, a1, #10 a1, a1, a1, lsr #2 a1, a1, a1, lsr #4 a1, a1, a1, lsr #8 a1, a1, a1, lsr #16 a1, a1, lsr #3 a3, a1, a1, asl #2 a2, a2, a3, asl #1 a1, a1, #1 a2, a2, #10 pc, lr ; Take argument in a1 returns quotient in a1, ; remainder in a2 pc, lr a2, a1 a3, a1, #2 a1, a3 a3, a1, #4 a1, a3 a3, a1, #8 a1, a3 a3, a1, #16 a1, a3 a1, #3 a3, a1, #2 a3, a1 a3, #1 a2, a3 a2, #10 %FT0 a1, #1 a2, #10 ; Take argument in a1 returns quotient in a1, ; remainder in a2 3-106 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER 4 -- -- -- -- MEMORY CONTROLLER OVERVIEW The S3C44B0X memory controller provides the necessary memory control signals for external memory access. S3C44B0X has the following features; Little/Big endian(selectable by an external pin) Address space: 32Mbytes per each bank (total 256MB:8 banks) Programmable access size(8/16/32-bit) for all banks Total 8 memory banks 6 memory banks for ROM, SRAM etc. 2 memory banks for ROM, SRAM, FP/EDO/SDRAM etc . 7 fixed memory bank start address and programmble bank size 1 flexible memory bank start address and programmable bank size Programmable access cycles for all memory banks External wait to extend the bus cycles Supports self-refresh mode in DRAM/SDRAM for power-down Supports asymmetrically or symmetrically addressable DRAM -- -- -- -- -- -- 4-1 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR 0x1000_0000 SROM/DRAM/SDRAM (nGCS7) 0x0e00_0000 SROM/DRAM/SDRAM (nGCS6) 0x0c00_0000 SROM (nGCS5) 0x0a00_0000 SROM (nGCS4) 0x0800_0000 SROM (nGCS3) 0x0600_0000 SROM (nGCS2) 0x0400_0000 SROM (nGCS1) 0x0200_0000 0x01c0_0000 0x0000_0000 32MB Special function Registers (4M bytes) SROM (nGCS0) 28MB 32MB 32MB 32MB 256MB SA[27:0] Accessable Region 32MB 2/4/8/16/32MB 2/4/8/16/32MB Refer to Table 4-1 NOTE: SROM means ROM or SRAM type memory Figure 4-1. S3C44B0X Memory Map after Reset Table 4-1. Bank 6/7 Address Address 2MB 4MB Bank 6 Start address End address 0xc00_0000 0xc1f_ffff 0xc00_0000 0xc3f_ffff Bank 7 Start address End address NOTE: 8MB 16MB 32MB 0xc00_0000 0xc7f_ffff 0xc00_0000 0xcff_ffff 0xc00_0000 0xdff_ffff 0xc20_0000 0xc3f_ffff 0xc40_0000 0xc7f_ffff 0xc80_0000 0xcff_ffff 0xd00_0000 0xdff_ffff 0xe00_0000 0xfff_ffff Bank 6 and 7 must have the same memory size. 4-2 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER FUNCTION DESCRIPTION LITTLE ENDIAN/BIG ENDIAN While nRESET is L, the ENDIAN pin defines which endian mode should be selected. If the ENDIAN pin is connected to Vss with a pull-down resistor, the little endian mode is selected. If the pin is connected to Vdd with a pull-up resistor, the big endian mode is selected. ENDIAN Input @Reset 0 1 ENDIAN Mode Little endian Big endian BANK0 BUS WIDTH The data bus width of BANK0 (nGCS0) should be configured as one of 8-bit,16-bit and 32-bit. Because the BANK0 is the booting ROM bank(map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will be determined by the logic level of OM[1:0] at Reset. OM1 (Operating Mode 1) 0 0 1 1 Programming Memory Controller All thirteen memory control registers have to be written using the STMIA instruction as shown in the following example; ldr ldmia ldr stmia DATA DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD r0, =SMRDATA r0, {r1-r13} r0, =0x01c80000 r0, {r1-r13} 0x22221210 0x00000600 0x00000700 0x00000700 0x00000700 0x00000700 0x00000700 0x0001002a 0x0001002a 0x00960000 + 953 0x0 0x20 0x20 OM0 (Operating Mode 0) 0 1 0 1 Booting ROM Data width 8-bit 16-bit 32-bit Test Mode ; BWSCON Address SMRDATA ; ; ; ; ; ; ; ; ; ; ; ; ; BWSCON GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6, EDO DRAM(Trcd=3, Tcas=2, Tcp=1, CAN=10bit) GCS7, EDO DRAM Refresh(REFEN=1, TREFMD=0, Trp=3, Trc=5, Tchr=3) Bank Size, 32MB/32MB MRSR 6(CL=2) MRSR 7(CL=2) 4-3 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR MEMORY(SROM/DRAM/SDRAM) ADDRESS PIN CONNECTIONS MEMORY ADDR. PIN A0 A1 A2 A3 ... S3C44B0X ADDR. @ 8-bit DATA BUS A0 A1 A2 A3 ... S3C44B0X ADDR. @ 16-bit DATA BUS A1 A2 A3 A4 ... S3C44B0X ADDR. @ 32-bit DATA BUS A2 A3 A4 A5 ... 4-4 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM BANK ADDRESS PIN CONNECTION Table 4-2. SDRAM Bank Address configuration Bank Size 2MByte Bus Width x8 x16 4MB x8 x16 x32 8MB x16 x32 x8 x8 x16 x16 x32 16MB x32 x8 x8 x16 x16 x32 x32 x8 x16 32MB x16 x16 x32 x32 x16 x32 x8 x16 256Mb 128Mb 64Mb 128Mb 16Mb 64Mb 64Mb 16Mb 16Mb Base Component 16Mbit Memory Configuration (1M x 8 x 2Bank) x 1 (512K x 16 x 2B) x 1 (2M x 4 x 2B) x 2 (1M x 8 x 2B) x 2 (512K x 16 x 2B) x 2 (2M x 4 x 2B) x 4 (1M x 8x 2B) x 4 (4M x 8 x 2B) x 1 (2M x 8 x 4B) x 1 (2M x 16 x 2B) x 1 (1M x 16 x 4B) x 1 (512K x 32 x 4B) x 1 (2M x 4 x 2B) x 8 (8M x 4 x 2B) x 2 (4M x 4 x 4B) x 2 (4M x 8 x 2B) x 2 (2M x 8 x 4B) x 2 (2M x 16 x 2B) x 2 (1M x 16 x 4B) x 2 (4M x 8 x 4B) x 1 (2M x 16 x 4B) x 1 (8M x 4 x 2B) x 4 (4M x 4 x 4B) x 4 (4M x 8 x 2B) x 4 (2M x 8 x 4B) x 4 (4M x 8 x 4B) x 2 (2M x 16 x 4B) x 2 (8M x 8 x 4B) x 1 (4M x 16 x 4B) x 1 A24 A[24:23] A24 A[24:23] A[23:22] A23 A[23:22] A23 A[23:22] A23 A[22:21] A22 A[22:21] A22 A21 Bank Address A20 4-5 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR ROM Memory Interface Example A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn Figure 4-2. Memory Interface with 8bit ROM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn Figure 4-3. Memory Interface with 8bit ROM x 2 4-6 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE0 A11 nOE A12 nGCSn A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE1 A11 nOE A12 nGCSn A13 A14 A15 A16 A17 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D16 D17 D18 D19 D20 D21 D22 D23 A2 A3 A4 A5 A6 A7 A8 A9 A10 nWBE2 A11 nOE A12 nGCSn A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D24 D25 D26 D27 D28 D29 D30 D31 nWBE3 nOE nGCSn Figure 4-4. Memory Interface with 8bit ROM x 4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn Figure 4-5. Memory Interface with 16bit ROM 4-7 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR SRAM Memory Interface Example A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0 Figure 4-6. Memory Interface with 16bit SRAM 4-8 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 nWE nOE nGCSn nBE2 nBE3 Figure 4-7. Memory Interface with 16bit SRAM x 2 4-9 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR DRAM Memory Interface Example A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 nRAS0 nCAS0 nCAS1 nWE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 nRAS nLCAS nUCAS nWE nOE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Figure 4-8. Memory Interface with 16bit DRAM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 nRAS0 nCAS0 nCAS1 nWE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 nRAS nLCAS nUCAS nWE nOE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 nRAS0 nCAS2 nCAS3 nWE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 nRAS nLCAS nUCAS nWE nOE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Figure 4-9. Memory Interface with 16bit DRAM x 2 4-10 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM Memory Interface Example A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A21 A22 DQM0 DQM1 SCKE SCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE Figure 4-10. Memory Interface with 16bit SDRAM (4Mx16, 4bank) A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A22 A23 DQM0 DQM1 SCKE SCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A22 A23 DQM2 DQM3 SCKE SCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE Figure 4-11. Memory Interface with 16bit SDRAM (4Mx16 * 2ea, 4bank) NOTE: Please refer to Table 4-2 the Bank Address configurations of SDRAM. 4-11 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER SPECIAL REGISGERS BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register BWSCON Address 0x01C80000 R/W R/W Description Bus Width & Wait Status Control Register Reset Value 0x000000 BWSCON ST7 Bit [31] Description This bit determines SRAM for using UB/LB for bank 7 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 7 (If bank7 has DRAM or SDRAM, WAIT function is not supported) 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 7 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 6 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 6 (If bank6 has DRAM or SDRAM, WAIT function is not supported) 0 = WAIT disable, 1 = WAIT enable These two bits determine data bus width for bank 6 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 5 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 5 0 = WAIT disable, 1 = WAIT enable These two bits determine data bus width for bank 5 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 4 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 4 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 4 00 = 8-bit 01 = 16-bit, 10 = 32-bit Initial state 0 WS7 [30] 0 DW7 ST6 [29:28] [27] 0 0 WS6 [26] 0 DW6 ST5 [25:24] [23] 0 0 WS5 DW5 ST4 [22] [21:20] [19] 0 0 0 WS4 DW4 [18] [17:16] 0 0 4-12 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) BWSCON ST3 Bit [15] Description This bit determines SRAM for using UB/LB for bank 3 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 3 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 3 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 2 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 2 0 = WAIT disable 1 = WAIT enable These two bits determine data bus width for bank 2 00 = 8-bit 01 = 16-bit, 10 = 32-bit This bit determines SRAM for using UB/LB for bank 1 0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] ) This bit determines WAIT status for bank 1 0 = WAIT disable, 1 = WAIT enable These two bits determine data bus width for bank 1 00 = 8-bit 01 = 16-bit, 10 = 32-bit Indicates data bus width for bank 0 (read only) 00 = 8-bit 01 = 16-bit, 10 = 32-bit The states are selected by OM[1:0] pins Indicates endian mode (read only) 0 = Little endian 1 = Big endian The states are selected by ENDIAN pins Initial state 0 WS3 DW3 ST2 [14] [13:12] [11] 0 0 0 WS2 DW2 ST1 [10] [9:8] [7] 0 0 0 WS1 DW1 DW0 [6] [5:4] [2:1] 0 0 - ENDIAN [0] - NOTES: 1. All types of master clock in this memory controller correspond to the bus clock. For example, MCLK in DRAM and SRAM is same as the bus clock, and SCLK in SDRAM is also the same as the bus clock. In this chapter (Memory Controller), one clock means one bus clock. 2. nBE[3:0] is the 'AND' signal nWBE[3:0] and nOE 4-13 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR BANK CONTROL REGISTER (BANKCONn: nGCS0-nGCS5) Register BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 Address 0x01C80004 0x01C80008 0x01C8000C 0x01C80010 0x01C80014 0x01C80018 R/W R/W R/W R/W R/W R/W R/W Description Bank 0 control register Bank 1 control register Bank 2 control register Bank 3 control register Bank 4 control register Bank 5 control register Reset Value 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 BANKCONn Tacs Bit [14:13] Description Address set-up before nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Chip selection set-up nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks 001 011 101 111 = = = = 2 clocks 4 clocks 8 clocks 14 clocks Initial State 00 Tcos [12:11] 00 Tacc [10:8] 111 Toch [7:6] Chip selection hold on nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address holding time after nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data 000 Tcah [5:4] 00 Tpac [3:2] 00 PMC [1:0] 00 4-14 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register BANKCON6 BANKCON7 Address 0x01C8001C 0x01C80020 R/W R/W R/W Description Bank 6 control register Bank 7 control register Reset Value 0x18008 0x18008 BANKCONn MT Bit [16:15] Description These two bits determine the memory type for bank6 and bank7 00 = ROM or SRAM 01 = FP DRAM 10 = EDO DRAM 11 = Sync. DRAM Initial State 11 Memory Type = ROM or SRAM [MT=00] (15-bit) Tacs [14:13] Address set-up before nGCS 00 = 0 clock 01 = 1 clock clocks Chip selection set-up nOE 00 = 0 clock 01 = 1 clock clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks 00 10 = 2 clocks 11 = 4 00 10 = 2 clocks 11 = 4 111 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks 00 Tcos [12:11] Tacc [10:8] Toch [7:6] Chip selection hold on nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address hold time on nGCSn 00 = 0 clock 01 = 1clock 10 = 2 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 10 = 8 consecutive accesses 01 = 4 consecutive accesses 11 = 16 consecutive accesses 11 = 4 clocks Tcah Tpac [5:4] [3:2] 00 00 PMC [1:0] 00 Memory Type = FP DRAM [MT=01] or EDO DRAM [MT=10] (6-bit) Trcd [5:4] RAS to CAS delay 00 = 1 clock 10 = 3 clocks CAS pulse width 0 = 1 clock CAS pre-charge 0 = 1 clock 00 01 = 2 clocks 11 = 4 clocks 0 1 = 2 clocks 0 1 = 2 clocks 00 Tcas Tcp CAN [3] [2] [1:0] Column address number 00 = 8-bit 01 = 9-bit 10 = 10-bit 11 = 11-bit 4-15 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) (Continued) Memory Type = SDRAM [MT=11] (4-bit) Trcd SCAN [3:2] [1:0] RAS to CAS delay 00 = 2 clocks 01 = 3 clocks Column address number 00 = 8-bit 01 = 9-bit 10 10 = 4 clocks 00 10= 10-bit SUPPORTED BANK 6/7 MEMORY CONFIGURATION Bank Bank7 Bank6 NOTE: Support SROM DRAM DRAM SROM SDRAM SROM SROM SDRAM Not support SDRAM DRAM DRAM SDRAM SROM means ROM or SRAM type memory REFRESH CONTROL REGISTER Register REFRESH Address 0x01C80024 R/W R/W Description DRAM/SDRAM refresh control register Reset Value 0xac0000 REFRESH REFEN TREFMD Bit [23] [22] Description DRAM/SDRAM Refresh Enable 0 = Disable 1 = Enable(self or CBR/auto refresh) DRAM/SDRAM Refresh Mode 0 = CBR/Auto Refresh 1 = Self Refresh In self-refresh time, the DRAM/SDRAM control signals are driven to the appropriate level. DRAM/SDRAM RAS pre-charge Time DRAM : 00 = 1.5 clocks 01 = 2.5 clocks 10 = 3.5 clocks 11 = 4.5 clocks SDRAM : 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not support SDRAM RC minimum Time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks CAS Hold Time(DRAM) 00 = 1 clock 01 = 2 clocks 10 = 3 clocks 11 = 4 clocks Not use DRAM/SDRAM refresh count value. Please, refer to chap. 6 DRAM refresh controller bus priority section. Refresh period = (211-refresh_count+1)/MCLK Ex) If refresh period is 15.6 us and MCLK is 60 MHz, the refresh count is as follows; refresh count = 211 + 1 - 60x15.6 = 1113 Initial State 1 0 Trp [21:20] 10 Trc Tchr Reserved Refresh Counter [19:18] [17:16] [15:11] [10:0] 11 00 0000 0 4-16 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER 4-17 MEMORY CONTROLLER S3C44B0X RISC MICROPROCESSOR BANKSIZE REGISTER Register BANKSIZE Address 0x01C80028 R/W R/W Description Flexible bank size register Reset Value 0x0 BANKSIZE SCLKEN Bit [4] Description SCLK will be generated only during SDRAM access cycle. This feature will reduce the power consumption. 1 is recommended. 0 = normal SCLK 1 = SCLK for reducing power consumption Not use BANK6/7 memory map 000 = 32M/32M 100 = 2M/2M 101 = 4M/4M 110 = 8M/8M 111 = 16M/16M Initial State 0 Reserved BK76MAP [3] [2:0] 0 000 SDRAM MODE REGISTER SET REGISTER (MRSR) Register MRSRB6 MRSRB7 Address 0x01C8002C 0x01C80030 R/W R/W R/W Description Mode register set register bank6 Mode register set register bank7 Reset Value xxx xxx MRSR Reserved WBL TM Bit [11:10] [9] [8:7] Not use Write burst length 0 is the recommended value Test mode 00: mode register set, 01, 10, 11: reserved Description Initial State - x xx CL [6:4] CAS latency 000 = 1 clock, 010 = 2 clocks, the others = reserved Burst type 0: Sequential (recommended) 1: N/A Burst length 000: 1 the others: N/A xxx 011=3 clocks x BT [3] BL [2:0] xxx NOTE: MRSR register must not be reconfigured while the code is running on SDRAM. IMPORTANT NOTES 1. 2. All 13 memory control registers have to be written using the STMIA instruction. In STOP mode/SL_IDLE mode, DRAM/SDRAM has to enter the DRAM/SDRAM self-refresh mode. 4-18 S3C44B0X RISC MICROPROCESSOR MEMORY CONTROLLER NOTES 4-19 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 5 CLOCK & POWER MANAGEMENT OVERVIEW The Clock Generator in S3C44B0X can generate the required clock signals for the CPU as well as peripherals. The Clock Generator can be controlled to supply or disconnect the clock to each peripheral block by S/W, which will reduce the power. As well as this kind of S/W controllability, S3C44B0X has various power management schemes to keep optimal power consumption for a given task. The power management in S3C44B0X consists of five modes : Normal mode, Slow mode, Idle mode, Stop mode and SL Idle mode for LCD. The Normal mode is used to supply clocks to CPU as well as all peripherals in S3C44B0X. In this case, the power consumption will be maximized when all peripherals are turned on. The user can control the operation of peripherals by S/W. For example, if a timer and DMA are not needed, the user can disconnect the clock to the timer and DMA to reduce power. The Slow mode is non-PLL mode. Unlike the Normal mode, the Slow mode uses an external clock directly as master clock in S3C44B0X without PLL. In this case, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL itself is excluded. The Idle mode disconnects the clock only to CPU core while it supplies the clock to all peripherals. By using this Idle mode, power consumption due to CPU core can be reduced. Any interrupt request to CPU can wake-up from Idle mode. The Stop mode freezes all clocks to the CPU as well as peripherals by disabling PLL. The power consumption is only due to the leakage current in S3C44B0X, which is less than 10 uA. The wake-up from Stop mode can be done by external interrupt to CPU. The SL Idle mode causes the LCD controller to work. In this case, the clock to CPU and all peripherals except LCD controller should be stopped, therefore, the power consumption in the SL Idle mode is less than that in the Idle mode. 5-1 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR FUNCTION DESCRIPTION CLOCK GENERATION Figure 5-1 shows a block diagram of the clock generator. The main clock source comes from an external crystal or external clock. The clock generator has an oscillator(Oscillation Amplifier) which should be connected to an external crystal, and also has a PLL (Phase-Locked-Loop) which takes the low frequency oscillator output as its input and generates the high frequency clock required by S3C44B0X. The clock generator block has the logic to generate a stable clock frequency after a reset or a stop mode. PWRDN XTAL0 EXTAL0 EXTCLK OSC 00 MUX Fin 01 MUX5 for Timer5 PLL Fpllo MUX MUX CLOCK CONTROL LOGIC 00,01 CLKout (External) Port E control Fout (MCLK) Test Mode only(10, 11) powerdown OM[3:2] Figure 5-1. Clock Generator Block Diagram CLOCK SOURCE SELECTION Table 5-1 shows the relationship between the combination of mode control pins (OM3 and OM2) and the selection of source clock for S3C44B0X. The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET. Table 5-1. Clock source selection at boot-up Mode OM[3:2] 00 01 Others(10, 11) Clock Source Crystal clock Ext. Clock Crystal Driver enable disable Test mode PLL starting state enable (1) Fout PLL Output (1) PLL Output (1) enable (1) NOTE: Although the PLL starts just after a reset, the PLL output can not be used as Fout until the S/W writes valid settings to the PLLCON register. Before this valid setting, the clock from crystal oscillator or Ext. clock source will be used as Fout directly. Even if the user wants to maintain the default value of PLLCON register, the user should write the same value into PLLCON register. If the S3C44B0X operates by PLL output from XTAL0 & EXTAL0, the EXTCLK can be dedicated as TCLK for Timer 5. 5-2 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT PLL (PHASE-LOCKED-LOOP) The PLL within the clock generator is the circuit which synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks (Figure 5-2 shows the clock generator block diagram); the VCO(Voltage Controlled Oscillator) to generate the output frequency proportional to input DC voltage, the divider P to divide the input frequency(Fin) by p, the divider M to divide the VCO output frequency by m which is input to PFD(Phase Frequency Detector), the divider S to divide the VCO output frequency by s which is Fpllo(the output frequency from PLL block), the phase difference detector, charge pump, and loop filter. The output clock frequency Fpllo is related to the reference input clock frequency Fin by the following equation: Fpllo = (m * Fin) / (p * 2 ) m = M (the value for divider M)+ 8, p = P(the value for divider P) + 2 The following sections describe the operation of the PLL, that includes the phase difference detector, charge pump, VCO (Voltage controlled oscillator), and loop filter. If the PLL is on, Fpllo is same as Fout as shown in Figure 5-1. Phase Difference Detector (PFD) The PFD monitors the phase difference between the Fref (the reference frequency as shown in Fig. 5-2) and Fvco (the output frequency from VCO and Divider M block) and generates a control signal(tracking signal) when it detects a difference. Charge Pump (PUMP) The charge pump converts the PFD control signal into a proportional charge in voltage across the external filter that drives the VCO. Loop Filter The control signal that the PFD generates for the charge pump, may generate large excursions(ripples) each time the Fvco output is compared to the Fref. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter consisting of a resistor and capacitor. A recommended capacitance in the external loop filter(Capacitance as shown in Figure 5-2) is 700pF. Voltage Controlled Oscillator (VCO) The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. When the Fvco output matches Fref in terms of frequency as well as phase, the PFD stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains locked onto the system clock. Usual Condition for PLL & Clock Generator The following conditions are generally used. Loop filter capacitance External feedback resistance External X-tal frequency External capacitance used for X-tal 700-820 pF 1Mohm 6-20 Mhz 15-22 pF s 5-3 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR PWRDN Fref PFD PUMP R C Fvco M[7:0] Divider M VCO Internal External Loop Filter Fin Divider P P[5:0] PLLCAP 700pF S[1:0] Divider S Fpllo Figure 5-2. PLL (Phase-Locked Loop) Block Diagram VDD or External Clock for Timer5 EXTCLK External OSC VDD EXTCLK XTAL0 XTAL0 EXTAL0 1Mohm EXTAL0 a) X-TAL oscillation b) External clock source Figure 5-3. Main Oscillator Circuit Examples 5-4 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used, i.e., the PLL clock or the direct OSC clock. When PLL is configured to a new frequency value, the clock control logic disables the FOUT until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wake-up from power-down mode. PLL Lock Time The lock time is the time required for PLL output stabilization. The lock time should be bigger than 208us. After reset and wake-up from STOP and SL_IDLE mode, respectively, the lock-time is inserted automatically by the internal logic with lock time count register. The automatically inserted lock time is calculated as follows; t_lock(the PLL lock time by H/W logic) = (1/ Fin) x n, (n = LTIMECNT value) Power-On Reset Figure 5-4 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the stabilization of OSC clock, the PLL starts to operate according to the default PLL configuration. However PLL is commonly known to be unstable after poweron reset, so Fin fed directly to Fout instead of the Fpllo(PLL output) before the S/W newly configures the PLLCON. Even if the user wants to use the default value of PLLCON register after Reset, the user should write the same value into PLLCON register by S/W. The PLL begins the lockup sequence again toward the new frequency only after the S/W configures the PLL with a new frequency. Fout can be configured to be PLL output(Fpllo) immediately after lock time. Power PLL can operate after OM[3:2] is latched. nRESET OSC PLL is configured by S/W first time. Clock Disable lock time VCO is adapted to new clock frequency. VCO output Fout The logic operates by OSC clcok. Fout is new frequency. Figure 5-4. Power-On Reset Sequence 5-5 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR Change PLL Settings In Normal Operation Mode During the operation of S3C44B0X in Normal mode, if the user wants to change the frequency by writing the PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal blocks in S3C440X. The timing diagram is as follow. PLL_CLK PMS setting PLL Lock-time FOUT It changes to new PLL clock after lock time automatically Figure 5-5. The Case that Changes Slow Clock by Setting PMS Value 5-6 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT POWER MANAGEMENT The power management block controls the system clocks by software for reduction of power consumption in S3C44B0X. These schemes are related to PLL, clock control logic, peripheral clock control, and wake-up signal. S3C44B0X has five power-down modes. The following section describes each power managing mode. The transition between the modes is not allowed freely. For available transitions among the modes, please refer to Figure 5-11. Normal Mode In normal mode, all peripherals(UART, DMA, Timer, and so on) and the basic blocks(CPU core, bus controller, memory controller, interrupt controller, and power management block) may operate fully. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by S/W to reduce power consumption. NOTE: The basic blocks consist of the CPU core, bus controller, memory controller, interrupt controller, and power management. IDLE Mode In IDLE mode, the clock to CPU core is stopped except bus controller, memory controller, interrupt controller, and power management block. To exit IDLE mode, EINT[7:0], or RTC alarm interrupt, or the other interrupts should be activated. (If users are willing to use EINT[7:0], GPIO block has to be turned on before the activation). STOP Mode In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit are also stopped. Just after exiting the STOP mode, only THAW mode is available. In other words, the user cannot return to NORMAL mode from STOP mode as shown in Fig. 5-11, directly. To exit from STOP mode, EINT[7:0] or RTC alarm interrupt has to be activated. Just after entering into the STOP mode, the Clock Control Logic output the Fin-clock, instead of the Fpllo-clock, from Fout during 16 Fin-clocks. After 16 Fin-clocks, the Fout is stopped and S3C44B0X enters into STOP mode completely. The latency time from command issue of the power down by STOP mode to actual entrance into power down mode is calculated as follows: Power down latency time = Input clock period (crystal oscillator clock or external clock) * 16 If S3C44B0X is in the SLOW mode, the S3C44B0X enters into STOP mode immediately because the frequency of the clock in slow mode is lower than Fin. The S3C44B0X can exit from STOP mode by external interrupts or RTC alarm interrupt. During the wake-up sequences, the crystal oscillator and PLL may begin to operate. The lock time is also needed to stabilize Fout. The lock time is inserted automatically and guaranteed by power management logic. During this lock time the clock is not supplied. Just after wake-up sequences wake-up interrupt(alarm or external interrupt) is requested. 5-7 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR Fin (X-tal) Wake-up Clock Disable VCO Output 16 OSC clocks Fout STOP mode is initiated. lock time Figure 5-6. Entering STOP Mode and Exiting STOP Mode (Wake-up) IMPORTANT NOTES Before entering STOP mode, the following 6 items must be obeyed. 1) DRAM has to be in self-refresh mode during STOP mode to retain valid memory data. 2) LCD display must be stopped before entering STOP mode because DRAM is in self-refresh mode and LCD can't access DRAM during DRAM self-refresh mode. If LCD display is turned on, SYSTEM will be hanged up. 3) The ports of S3C44B0X must be configured properly according to your system to reduce power consumption. 4) Before entering STOP mode the CPU must be in SLOW mode with PLL on. The PLL will be turned off automatically in STOP mode. 5) For the period of entering into STOP mode, if there is any wake-up request at last 3rd clock edge before the CPU goes into STOP mode, S3C44B0X will never respond to that wake-up source. For example, if EIN0 is asserted at that point, the EINT0 cannot wake up the system anymore, however other sources can wake up the system and then the EINT0 can be used for wake-up source in the next time. So, it is strongly recommended that any wake-up signals should not be asserted until entering into STOP mode completely. If your application cannot prevent wake-up request at that clock, please refer to the workaround document, which is located on our web sight. 5-8 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT Start slow with PLL on Wake up request should not occur here Enter into STOP mode FOUT 6) When S3C44B0X enters STOP mode, MCLK should be more than 2.5 times of Fin (X-tal frequency). After wake-up (in NORMAL mode), user can change MCLK to the frequency that user want. For example, if Fin is 20MHz and a user want MCLK=36MHz, the MCLK before entering into STOP mode should be more than 50MHz. After wake-up and S3C44B0X returns to NORMAL mode from STOP mode, MCLK can be changed from 50MHz to 36MHz by setting PLLCON register. 7) When S3C44B0X enters STOP mode in the level triggered EINT mode, the level EINT wake-up should not be active. If the level EINT wake-up is active, S3C44B0X should skip entering into STOP mode. SL_IDLE Mode (S_LCD Mode) In SL_IDLE mode, the clock to the basic blocks is stopped. Only the LCD controller is working to maintain the LCD screen. Less power is consumed in the SL_ILDE mode than in the IDLE mode. Before entering into SL_IDLE mode, SLOW mode has to be entered and PLL has to be turned off. After SLOW mode entrance and PLL-off, 0x46(LCDC enable, IDLE enable, and SL_IDLE enable)should be written into the CLKCON register to enter into SL_IDLE mode. To exit SL_IDLE mode, EINT[7:0] or RTC alarm interrupt has to be activated. In this case, the processor mode will change into Slow Mode automatically as shown in Fig. 5-11. To return to Normal mode, users have to wait until the end of lock time, then disable the SLOW mode and clear the SL_IDLE bit. In the PLL lock time, the SLOW clock is supplied. DRAM has to be in self-refresh mode during SL_IDLE mode to retain the valid data in DRAM. S/W Lock time PLL_CLK SLOW_BIT Wake_Up PLL off SL_IDLE FOUT Devided OSC clock It changes to PLL clock after slow mode is disabled SL_IDLE enable Slow mode enable Wake_Up is accured by Alarm or EINT[7:0] PLL off Slow mode disable after lock time PLL on SL_IDLE mode is end Figure 5-7. Entering SL_IDLE Mode and Exiting SL_IDLE Mode (Wake-up) 5-9 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR SLOW Mode (non-PLL Mode) Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL, itself. The Fout is the frequency of divide_by_n of Fin without PLL. The divider ratio is determined by SLOW_VAL in the CLKSLOW control register. Fout = Fin / ( 2 x SLOW_VAL ), when SLOW_VAL is bigger than 0 Fout = Fin , when SLOW_VAL is 0 In SLOW mode, the PLL will be turned off to reduce the PLL power consumption. When PLL is turned off in SLOW mode and users change power mode from SLOW mode to NORMAL mode, the PLL needs clock stabilization time(PLL lock time). This PLL stabilization time is automatically inserted by the internal logic with lock time count register. The PLL stability time will take 400us after PLL is turn on. During PLL lock time, the Fout is SLOW clock. Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during SLOW mode. The timing diagram is as follow. PLL_CLK Slow bit PLL off FOUT Divided OSC clock It changes to PLL clock after slow mode off Slow mode enable Slow mode disable Figure 5-8. The Case that Exit_from_Slow_Mode Command is Issued in PLL on State If users exit from SLOW mode to Normal mode by disabling the SLOW mode bit in the CLKSLOW register after PLL lock time, the frequency is changed just after SLOW mode is disabled. The timing diagram is as follow. S/W lock time PLL_CLK Slow bit PLL off FOUT Divided OSC clock It changes to PLL clock after slow mode off Slow mode enable PLL off Slow mode disable PLL on Figure 5-9. The Case that Exit_from_Slow_Mode Command is Issued after Lock Time is End 5-10 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT If users exit from SLOW mode to Normal mode by disabling SLOW mode bit and PLL off bit simultaneously in CLKSLOW register, the frequency is changed just after the PLL lock time. The timing diagram is as follow. H/W lock time PLL_CLK Slow bit PLL off FOUT Divided OSC clock It changes to PLL clock after lock time automatically Slow mode enable PLL off Slow mode disable PLL on Figure 5-10. The Case that Exit_from_Slow_Mode Command is Issued the Instant PLL_on Command is Issued. Wake-Up & THAW State When the S3C44B0X is woken up from power down mode(STOP mode) by an EINT[7:0] or a RTC alarm interrupt, the processor state will be changed into THAW state as shown in Figure 5-11. In thaw state, the configuration of the CLKCON should be ignored because the CLKCON value, which had been set before the entrance to stop mode, can not reflect the actual processor state. After the wake-up from STOP mode, the processor is in THAW mode as explained above. The new value, which reflects the new state, has to be re-written into the CLKCON register. Eventually, the processor state will be changed from THAW state to Normal or SLOW or even STOP mode. Just after writing the valid configuration value into the CLKCON, the mode returns to normal mode, slow mode, or even STOP mode. Table 5-2. The Status of PLL and Fout after Wake-Up Mode before wake-up STOP SL_IDLE IDLE Signaling EINT[7:0] For Wake-Up The S3C44B0X can be woken up from SL_IDLE mode or STOP mode only if the following conditions are met. a) Level signal(H or L) or edge signal(rising or falling or both) is asserted on EINTn input pin. b) EINTn pin has to be configured as EINT in PCONG register. It is important to configure the EINTn in the PCONG register as an external interrupt pins. For wake-up, we need H/L level or rising/falling edge or both edge signals on EINTn pin. Just after wake-up the corresponding EINTn pin will not be used for wake-up. This means that these pins can be PLL on/off after wake up off on - unchanged Fout after wake up and before the lock time no clock slow mode clock unchanged Fout after the lock time by internal logic normal mode clock - unchanged 5-11 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR used as external interrupt request pins again. Entering IDLE Mode If CLKCON[2] is set to 1 to enter the IDLE mode, S3C44B0X will enter into IDLE mode after some delay(until when the power control logic receives ACK signal from the CPU wrapper). PLL On/Off The PLL can only be turned off for power saving in slow mode. If PLL is turned off in any other mode, MCU operation is not guaranteed. When the processor is in SLOW mode and tries to change its state into other state requiring that PLL be turned on, then SLOW_BIT should be clear to move to another state after PLL stabilization. PUPS register and STOP/SL_IDLE mode In STOP/SL_IDLE mode, the data bus(D[31:0] or D[15:0] ) is Hi-z state. But, because of the characteristics of I/O pad, the data bus pull-up resistors have to be turned on to reduce the power consumption in STOP/SL_IDLE mode. D[31:16] pin pull-up resistors can be controlled by PUPC and PUPD registers. D[15:0] pin pull-up resistors can be controlled by the PUPS register. OUTPUT PORT State and STOP/SL_IDLE mode If output is L, the current will be consumed through the internal parasitic resistance; if the output is H, the current will not be consumed. If a port is configured as an output port, the current consumption can be reduced if the output state is H. The output ports are recommended to be in H state to reduce STOP mode current consumption. ADC Power Down The ADC has an additional power-down bit in ADCCON. If S3C44B0X enters the STOP mode, the ADC should enter it's own power-down mode. 5-12 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT POWER MANAGEMENT STATE MACHINE SL_IDLE_BIT=1 SL_IDLE EINT[7:0] ,RTC alarm IDLE_BIT=1 IDLE Interrupts, EINT[7:0], RTC alarm NORMAL (SLOW_BIT=0) SLOW (SLOW_BIT=1) IDLE_BIT=0, STOP_BIT=0 & SLOW_BIT=0 THAW state STOP_BIT=1 PLL_OFF=0 & SLOW_BIT=1 SLOW (PLL on) STOP_BIT=1 EINT[7:0] RTC alarm STOP Figure 5-11. Power Management State Machine 5-13 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER PLL CONTROL REGISTER (PLLCON) Fpllo = (m * Fin) / (p * 2 ) m = (MDIV + 8), p = (PDIV + 2), s = SDIV NOTE: Fpllo must be greater than 20Mhz and less than 66Mhz. s Example If Fin=14.318Mhz and Fout=60Mhz, the calculated value is as follows; MDIV=59, PDIV=6 and SDIV=1 (This value may be calculated using PLLSET.EXE utility, provided by SAMSUNG. ) PLL VALUE SELECTION GUIDE 1. Fpllo * 2 has to be less than 170 MHz. 2. S should be as great as possible. 3. (Fin / p) is recommended to be 1Mhz or above. But, (Fin / p) < 2Mhz. s Register PLLCON PLLCON MDIV PDIV SDIV Address 0x01D80000 Bit [19:12] [9:4] [1:0] R/W R/W Description PLL configuration Register Description Main divider control Pre-divider control Post divider control Reset Value 0x38080 Initial State 0x38 0x08 0x0 5-14 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT CLOCK CONTROL REGISTER (CLKCON) Register CLKCON Address 0x01D80004 R/W R/W Description Clock generator control Register Reset Value 0x7ff8 CLKCON IIS IIC ADC RTC Bit [14] [13] [12] [11] Description Controls MCLK into IIS block 0 = Disable, 1 = Enable Controls MCLK into IIC block 0 = Disable, 1 = Enable Controls MCLK into ADC block 0 = Disable, 1 = Enable Controls MCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive. 0 = Disable, 1 = Enable Controls MCLK into GPIO block Set to 1 to use interrupt requests by EINT[4:7] 0 = Disable, 1 = Enable Controls MCLK into UART1 block 0 = Disable, 1 = Enable Controls MCLK into UART0 block 0 = Disable, 1 = Enable Controls MCLK into BDMA block 0 = Disable, 1 = Enable ( If BDMA is turned off, the peripherals in the peripheral bus may not be accessed ) Initial State 1 1 1 1 GPIO [10] 1 UART1 UART0 BDMA0,1 [9] [8] [7] 1 1 1 LCDC SIO ZDMA0,1 PWMTIMER IDLE BIT SL_IDLE [6] [5] [4] [3] [2] [1] Controls MCLK into LCDC block 0 = Disable, 1 = Enable Controls MCLK into SIO block 0 = Disable, 1 = Enable Controls MCLK into ZDMA block 0 = Disable, 1 = Enable Controls MCLK into PWMTIMER block 0 = Disable, 1 = Enable Enters IDLE mode. This bit can't be cleared automatically. 0 = Disable, 1 = Transition to IDLE(SL_IDLE) mode SL_IDLE mode option. This bit can't be cleared automatically. 0 = Disable, 1 = SL_IDLE mode. To enter SL_IDLE mode, CLKCON register has to be 0x46. Enters STOP mode. This bit can't be cleared automatically. 0 = Disable 1 = Transition to STOP mode 1 1 1 1 0 0 STOP BIT [0] 0 5-15 CLOCK & POWER MANAGEMENT S3C44B0X RISC MICROPROCESSOR CLOCK SLOW CONTROL REGISTER (CLKSLOW) Register CLKSLOW Address 0x01D80008 R/W R/W Description Slow clock control register Reset Value 0x9 CLKSLOW PLL_OFF Bit [5] Description 0 : PLL is turned on. PLL is turned on only when SLOW_BIT is 1. After PLL stabilization time (minimum 150uS), SLOW_BIT may be cleared to 0. 1 : PLL is turned off. PLL is turned off only when SLOW_BIT is 1. Initial State 0x0 SLOW_BIT [4] 0 : Fout = Fpllo (PLL output) 1: Fout = Fin / (2 x SLOW_VAL), (SLOW_VAL > 0) Fout = Fin, (SLOW_VAL = 0) 0x0 SLOW_VAL [3:0] The divider value for the slow clock when SLOW_BIT is on. 0x9 LOCK TIME COUNT REGISTER (LOCKTIME) Register LOCKTIME Address 0x01D8000C R/W R/W Description PLL lock time count register Reset Value 0xfff LOCKTIME LTIME CNT Bit [11:0] PLL lock time count value Description Initial State 0xfff 5-16 S3C44B0X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT NOTES 5-17 S3C44B0X RISC MICROPROCESSOR CPU WRAPPER & BUS PRIORITIES 6 CPU WRAPPER & BUS PRIORITIES OVERVIEW The CPU wrapper consists of a cache, write buffer, and CPU core. The bus arbitration logic determines the priority of each bus master. The CPU wrapper has an 8-Kbyte internal memory. The internal memory can be used in three ways. First the 8Kbyte memory can be used as an 8KB unified (instruction/data) cache. Second, the internal memory can be used as a 4-Kbyte unified cache and a 4-Kbyte internal SRAM. Third, the internal memory can be used wholly as an 8-Kbyte internal SRAM. The internal unified (instruction/data) cache adopts four-way set associative architecture with a four-word (16 bytes) line size. It has a write-through policy to keep data coherency. When a cache miss occurs, four words of memory are fetched sequentially from external memory. It has an LRU (Least Recently Used) algorithm to raise the hit ratio. The unified cache deals with instruction and data by distinguishing them. The internal SRAM mainly will be used to reduce ISR(interrupt service routine) execution time. ISR execution time will be reduced because the internal SRAM has the fastest access time. Also, the ISR in SRAM is very efficient because most ISR codes may cause cache-miss. The bus arbitration logic can determine the priorities of bus masters. The bus arbitration logic supports a round-robin priority mode and a fixed priority mode. Also, The priorities among LCD_DMA, BDMA, ZDMA, nBREQ (external bus masters) can be changed by S/W. 6-1 6-2 31 28 27 11 10 43210 17 Height = 128 Seg3 Tag Seg2 Tag Seg1 Tag Seg0 Tag 17 17 17 LRU Decoder 7 17 17 17 17 Instr3 Instr2 Instr1 Instr0 Instr3 Instr2 Instr1 Instr0 Instr3 Instr2 Instr1 Instr0 7 32 32 32 32 S3C44B0X RISC MICROPROCESSOR 32 CPU WRAPPER & BUS PRIORITIES Instr3 Instr2 Instr1 Instr0 Figure 6-1. Cache Memory Configuration Select Set S3C44B0X RISC MICROPROCESSOR CPU WRAPPER & BUS PRIORITIES CACHE OPERATION Cache Organization S3C44B0X cache has an 8KB (or 4KB) cache memory, four Tag RAMs and one LRU memory. The internal unified (instructions/data) cache adopts a four-way set associative architecture with 4-word (16 bytes) line size. It has a write-through policy to keep data coherency. It has an LRU (Least Recently Used) algorithm to raise the hit ratio. Cache Replace Operation After a system is initialized, the value of CS is set to "0000", signifying that the contents of set 0, set1, set2 and set 3 cache memories are invalid. When a cache fill occurs, the value of CS is changed to "0110" at the specified line, which signifies that only set 0 is valid. When the subsequent cache fill occurs, the value of CS will be "0011" at the specified line, which represents that contents of both set 0 and set 2 are valid. When the subsequent cache fill occurs, the value of CS will be "0101" at the specified line, which represents that contents of set 0, set 1, and set 2 are valid. And succesive cache fill make CS "1000" at the specified line, which represents that all caches are valid. The value of CS "1xxx" represents that all of the sets are valid. Then the next cache miss occurs, the least significant 3 bits of CS select set are replaced. First bit selects a group of sets. "0" selects group 0 (which contains set0 and set1 ) , otherwise group1 (which contains set2 and set3 ). Second bit selects the set of group 0 . "0" selects set0, otherwise set1. Third bit selects the set of group 1. "0" selects set2, otherwise set 3. For example, if LS 3bit is 000, the victim is set0. If LS 3bit is "101", the victim is set3. Cache Line Replacement All 4 Lines in the set valid Yes No Replace Invalid Line S0 = 0? L0 or L1 least resently used Yes S1 = 0? No Yes L2 or L3 least resently used S2 = 0? No Replace Line L0 Replace Line L1 Replace Line L2 Replace Line L3 Figure 6-2. Cache Replace Configuration 6-3 CPU WRAPPER & BUS PRIORITIES S3C44B0X RISC MICROPROCESSOR Cache Disable Operation The S3C44B0X cache provides the entire-cache-enable/disable mode. You can enable cache by setting the value of CM in SYSCFG to 01 or 11, and disable it by clearing SYSCFG[2:1] to 00. When the cache disable mode is specified, instructions and data are always fetched from external memory. The S3C44B0X can also provide noncacheable areas in cache-enable-mode for some particular memory access operations, such as the DMA operation. The two non-cacheable areas are specified by four special registers to be introduced later. Data coherency is important when the cache memory is re-enabled because the cache memory does not have auto flush mode. You also have to be cautious whether or not DMA changes memory data. The DMA accessible memory area should be non-cacheable to keep data coherency. To keep data coherency between cache and external memory, S3C44B0X uses the write-through method. Cache Flushing A cache flushing can re-enable the cache operation. When the cache is disabled, the LRU RAM can be manipulated exactly like normal memory. The cache can be flushed by writing 0 to the LRU RAM and making all cache data invalid. The memory location of the LRU memory is as follows: NOTE Cache flushing must be executed only in the cache disable mode. Non-Cacheable Area The S3C44B0X provides two non-cacheable areas. Each of them requires two cache control fields, which indicate the start and end address of each non-cacheable area. In a non-cacheable area, the cache is not updated when cache misses a read. Usually a cache stores any data in the whole system memory area, but sometimes it needs a non-cacheable area because the cache cannot keep track of the external memory device whose contents are changed without read/write operation. The size of a non-cacheable area can be increased/decreased by 4KB units. The end address has to point the next 4KB block. For example, if non-cacheable area is 0x10000~0x22fff, the start address value of NCACHBEn is 0x10 and the end address value of NCACHBEn is 0x23. To Speed Up a Program Execution by Considering Cache Usage 1. 2. 3. 4. Locates the ISRs, which is executed most frequently, on the internal SRAM. Let ISR not be cached. Most ISR codes cause a cache miss, and the codes in the cache memory are not re-used because the code is erased by main codes, executed after exiting the ISR. Locates the functions which are related to each other together and executes them concurrently. This function aggregation reduce cache misses. Somtimes, if the data area is assigned as non cachable area, the program execution speed will be higher, because most variables are not re-used. Refreshing the 16 byte cache memory is wasteful for un-reused variables. 6-4 S3C44B0X RISC MICROPROCESSOR CPU WRAPPER & BUS PRIORITIES INTERNAL SRAM (INTERNAL MEMORY MAP) S3C44B0X has a maximum 8 KB 4way set associative cache or internal SRAM. If the internal SRAM is 4 KB, the other 4KB internal memory can be used as a 2 way set associative cache. The memory access cycle of the internal SRAM is 1 MCLK cycle. Cache Size 8KB (4way) 4KB (2way) None SRAM Size None 4KB 8KB 4 way set associative 2 way set associative SRAM uses the area allocated for sets 2 and 3 of 8KB cache. 4 way set associative Note Addresses in a set memory is increased sequentially and addresses in TAG/LRU increases of 16byte. Don't access the interval addresses between 0x10003004 and 0x1000300f . Area(Set/Cache) cache set 0 cache set 1 cache set 2 cache set 3 cache tag 0 cache tag 1 cache tag 2 cache tag 3 LRU NOTE: Memory Map Address 0x10000000 - 0x100007ff 0x10000800 - 0x10000fff 0x10001000 - 0x100017ff 0x10001800 - 0x10001fff 0x10002000 - 0x100027f0 0x10002800 - 0x10002ff0 0x10003000 - 0x100037f0 0x10003800 - 0x10003ff0 0x10004000 - 0x100047f0 Size 2KB 2KB 2KB 2KB 512bytes (note) 512bytes (note) 512bytes (note) 512bytes (note) 512bytes (note) The cache tag3:0 & LRU must be read/written by word access (32bit). The address bit[3:0] of .tag & LRU must be 0. For example, if you want to read the 2nd item among 128 cache tag 0 items, you should not read the address 0x10002004, but 0x10002010. Therefore, the tag0 addresses are 0x10002000, 0x10002010, 0x10002020,..., 0x100027f0. 0x1000_0000 Valid data 0x1000_0010 Valid data 0x1000_0020 . . . Valid data 0x1000_07f0 Valid data 0x1000_0800 Set 0 (2KB) 0x1000_2000 0x1000_2010 0x1000_2020 . . . Valid data 0x1000_27f0 0x1000_2800 1 word (valid) 3 word (invalid) Tag0 (512B) Size 2KB 4 word 6-5 CPU WRAPPER & BUS PRIORITIES S3C44B0X RISC MICROPROCESSOR Figure 6-3. Cache Memory Mapping WRITE-BUFFER OPERATION Write Buffer Operation S3C44B0X has four write buffer registers to enhance memory writing performance. When the write buffer mode is enabled, the CPU writes data into the write buffer registers instead of an external memory even when the external bus is already occupied by another bus master like DMA. The write buffer block will write the data when the system bus is not occupied by higher priority bus masters. Also, CPU performance will be enhanced because the CPU does not have to wait the completion of the write operation. The write buffer has 4 registers. Each register includes a 32-bit data field, a 28-bit address field, and a 2-bit status field. 27 Address 0 MAS 31 Write Buffer Data 0 [31:0] Write Buffer Data Data to be written into external memory [1:0] MAS 00 = 8-bit data mode 01 = 16-bit data mode 10 = 32-bit data mode 11 = Not used [27:0] Address Indicates the address of write data Figure 6-4. Write Buffer Configuration 6-6 S3C44B0X RISC MICROPROCESSOR CPU WRAPPER & BUS PRIORITIES BUS PRIORITY MAP In S3C44B0X, there are seven bus masters, LCD_DMA, BDMA0, BDMA1, ZDMA0, ZDMA1, nBREQ (external bus masters), and CPU wrapper. The priorities among these bus masters after a reset are as follows; 1. DRAM refresh controller 2. LCD_DMA 3. ZDMA0,1 4. BDMA0,1 5. External bus master 6. Write buffer 7. Cache & CPU The bus priorities among LCD_DMA, ZDMA, BDMA, and an external bus master can be programmed by the SBUSCON register. The CPU wrapper always has the lowest priority regardless of the SBUSCON register. The round-robin priority mode or fixed priority mode can be selected. In the round-robin priority mode, the bus master which had once served will have the lowest priority. In this way, all the bus masters have equal priorities. In the fixed priority mode, each bus master's priority is written onto SBUSCON. SBUSCON determines which is 1st 4th priority bus master. 6-7 CPU WRAPPER & BUS PRIORITIES S3C44B0X RISC MICROPROCESSOR CPU WRAPPER SPECIAL REGISTERS There are 3 control registers for the CPU wrapper block (cache, write buffer, and ARM7TDMI). SYSCFG register controls the general system operation. NCACHBE0 & NCACHBE1 registers provide non-cacheable areas. SYSTEM CONFIGURATION REGISTER (SYSCFG) Register SYSCFG Address 0x01C00000 R/W R/W Description System Cofiguration Register Reset Value 0x01 SYSCFG Reserved Reserved DA(reserved) RSE(reserved) Bit [7] [6] [5] [4] Reserved to 0 Reserved to 0 Description Initial State 0 0 0 0 DATA ABORT controls. This bit is recommended to be 0. 0: Enable data abort 1: Disable data abort Enable read stall option. This bit is recommended to be 0. 0: read stall disable 1: read stall enable (Read stall option: Insert one internal wait cycle when reading data for cache & CPU core.) WE [3] This bit determines write buffer enable / disable. Some external devices, which require the minimum writing cycle time, do not operate normally because the period between consecutive writings is shortened the write buffer. 0 = Disable write buffer operation 1 = Enable write buffer operation These two bits determine cache mode 00 = Disable cache (8KB internal SRAM) 01 = Half cache enable (4KB cache, 4KB internal SRAM) 10 = Reserved 11 = Full Cache enable (8KB cache) Enable stall option. This bit is recommended to be 0. 0:stall disable 1:stall enable (Stall option: Insert one internal wait cycle when a nonsequential address is generated for caching) 0 CM [2:1] 00 SE [0] 1 6-8 S3C44B0X RISC MICROPROCESSOR CPU WRAPPER & BUS PRIORITIES NON-CACHEABLE AREA CONTROL REGISTER (NCACHBEn) Register NCACHBE0 NCACHBE1 Address 0x01C00004 0x01C00008 R/W R/W R/W Description Start address & end address of non-cacheable area 0 Start address & end address of non-cacheable area 1 Reset Value 0x00000000 0x00000000 NCACHBE0 SE0 Bit [31:16] Description End address of non-cacheable area 0. These 16 bits provide the end address of non-cacheable area 0. The minimum non-cacheable area is 4 Kbytes. SE0 = (End address + 1)/4K Initial State 0x0000 SA0 [15:0] Start address of non-cacheable area 0. These 16 bits provide the start address of non-cacheable area 0. SA0 = Start address/4K 0x0000 NCACHBE1 SE1 Bit [31:16] Description End address of non-cacheable area 1 These 16 bits provide the end address of non-cacheable area 1. The minimum non-cacheable area is 4Kbytes. SE1 = (End address + 1)/4K Initial State 0x0000 SA1 [15:0] Start address of non-cacheable area 1. These 16 bits provide the start address of non-cacheable area 1. The minimum non-cacheable area is 4Kbytes. SA1 = Start address/4K 0x0000 6-9 CPU WRAPPER & BUS PRIORITIES S3C44B0X RISC MICROPROCESSOR BUS PRIORITY SPECIAL REGISTER SYSTEM BUS PRIORITY CONTROLLER (SBUSCON) Register SBUSCON Address 0x01C40000 R/W R/W Description Determines the bus priorities among the bus masters Reset Value 0x80001B1B SBUSCON FIX S_LCD_DMA S_ZDMA S_BDMA S_nBREQ LCD_DMA ZDMA BDMA nBREQ NOTE: Bit [31] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 0: round-robin priorities 1: fixed priorities Description Initial State 0x1 00 01 10 11 00 01 10 11 Indicates the LCD_DMA bus priority (read only) 00: 1st 01: 2nd 10: 3rd 11: 4th Indicates the ZDMA bus priority (read only) 00: 1st 01: 2nd 10: 3rd 11: 4th Indicates the BDMA bus priority (read only) 00: 1st 01: 2nd 10: 3rd 11: 4th Indicates the nBREQ bus priority (read only) 00: 1st 01: 2nd 10: 3rd 11: 4th Determines the LCD_DMA bus priority 00: 1st 01: 2nd 10: 3rd 11: 4th Determines the ZDMA bus priority 00: 1st 01: 2nd 10: 3rd 11: 4th Determines the BDMA bus priority 00: 1st 01: 2nd 10: 3rd 11: 4th Determines the nBREQ bus priority 00: 1st 01: 2nd 10: 3rd 11: 4th The priorities are only valid in the fixed priority mode. 6-10 S3C44B0X RISC MICROPROCESSOR DMA 7 DMA OVERVIEW The S3C44B0X has 4 channel DMA Controllers. The two DMAs(we call it ZDMA : General DMA) are attached to SSB (Samsung System Bus) and the other two DMAs(we call it as BDMA : Bridge DMA) are inside the bridge, which is an interface layer between SSB and SPB (Samsung Peripheral Bus). The two ZDMA controllers attached to SSB are to transfer data from memory to memory, from memory to I/O memory(Fixed destination), and from I/O devices and I/O devices to memory. The other two BDMA controllers transfer data from memory to I/O devices and I/O devices to memory. In this case, I/O devices means the peripherals, attached to SPB like SIO, IIS and UART. The main advantage of DMA is that it can transfer the data without CPU intervention. The operation of ZDMA and BDMA can be initiated by S/W, the request from internal peripherals or the external request pins (nXDREQ0,1). The most important feature in ZDMA is the on-the-fly mode, which reduces the number of cycles during DMA operation between external memory and a fixed external peripheral (Fixed source or destination addressed device). Usually, the DMA transfer consists of two separate cycles, one is 'Read' from the source memory or I/O device and the other is 'Write' to memory or destination I/O device. To perform these operations, the memory controller reads the data on data bus and writes this data to data bus, again. The on-the-fly-mode has inseparable Read/Write cycle. In other words, the memory controller generates the acknowledge signal for the source or destination device to read or write data on the data bus. At the same time, the memory controller also generates the Read or Write-related control signals for memory access. This kind of on-the-fly-mode can reduce the number of required DMA cycles, different from the general DMA cycles, which has separate Read and Write cycles. To operate the on-the-fly mode, the bus size of the source should be the same as that of the destination. 7-1 DMA S3C44B0X RISC MICROPROCESSOR ZDMA/BDMA OPERATION ZDMA (GENERAL DMA) Figure 7-1 shows the internal diagram of a ZDMA block. The ZDMA is interfaced to SSB and can transfer data from external memory to external memory. Unlikely the BDMA(Bridge DMA), this DMA can be used to transfer data between memory-mapped device or memories. In other words, data transfer between fixed source and external memory, external memory and external memory, and external memory and fixed destination can be done by using this DMA. The DMA operation can be started by S/W or an external DMA request signal, which will be explained later. In the ZDMA, there is a temporary buffer which allows multiple transfers to enhance bus utilization as well as transfer speed. In other words, the S3C44B0X has a 4-word FIFO-type buffer to support the 4-word burst transfer during DMA operation. For example, during the DMA operation between memories, a 4-word burst write happens after a 4-word burst read. SSB SBS_Signals SBS_STATE FIFO (4-WORD) ZDMA 0 ZDMA 1 Channel Arbiter ZDMA Control Figure 7-1. ZDMA Controller Block Diagram Source Selector Source Selector nXDREQ[0], nXACK[0] nXDREQ[1], nXACK[1] 7-2 S3C44B0X RISC MICROPROCESSOR DMA BDMA (BRIDGE DMA) Figure 7-2 shows the internal diagram of a BDMA block. The BDMA is in the Bridge, which is the interface layer between SSB and SPB. The main role of BDMA is to transfer the data between external memory and internal peripherals like UART, IIS and SIO, which are attached to SPB. The timer can also request a DMA operation anytime; it is useful for operating the ADC block automatically. Usually, the CPU or other master devices should access the external memory through memory controller, which is attached to SPB. Please be reminded that the BDMA is also a type of master device. To transfer the data from memory (peripheral devices) to peripheral devices (memory) attached to SPB (SSB), the memory controller attached to SSB should be used. Because the BDMA is in the Bridge, which is an interface layer between SSB and SPB, it can transfer the data between two devices, which are attached to SSB as well as SPB. The BDMA cannot support a 4-word burst transfer (the block transfer mode) because BDMA does not have a temporary buffer and because the peripheral devices attached to SPB is slow. Specifically, the BDMA can support the data transfer from external memory to external memory, a slightly ineffective way of data transfer if you look at the block diagram. Even if BDMA can support the data transfer between external memories, ZDMA is recommended for use instead of to transfer data between external memories faster transfer and optional bus utilization are required. But, if more number of DMA channels for data transfer between external memories (Maximum 2 channels using ZDMA) is needed, the BDMA can be used. SSB BDMA 0 SBS_Signals BDMA 1 Channel Arbiter BDMA Control x UART1 TIMER Source Selector x UART0 IIS SIO SBS_STATE SLAVE Peripheral Source Selector SPB_Sginals SPB Figure 7-2. BDMA Controller Block Diagram 7-3 DMA S3C44B0X RISC MICROPROCESSOR EXTERNAL DMA REQ/ACK PROTOCOL There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like DMA request and acknowledge are related to these protocols. Because ZDMA and BDMA can support external triggering, these protocols correspond to ZMDA only, not BDMA. Handshake Mode In the handshake mode, the DMA can generate a single DMA acknowledge corresponding to the single DMA request. The Figure 7-3 shows the handshake mode of DMA operation. In this figure, the DMA service means a paired or an inseparable Read and Write cycle during DMA operation, which is one DMA operation. During one DMA operation (Pared or inseparable Read and Write cycle), the bus controller does not allocate bus usage right to other bus masters. If the user wants to allocate the bus usage properly for the higher priority master during one DMA operation, the user should use the single step mode, which is explained in the next page. The single step mode considers one DMA operation to consist of separable Read and Write cycle. It means that the bus controller can allocate the bus usage to other higher bus master between Read and Write cycle. The DMA request by nXDREQ causes one byte, one half word, or one word to be transmitted. The handshake mode requires the DMA request for every data transfer. The nXDREQ can be released after active nXDACK and request again after inactive nXDACK as shown in Figure 7-3. nXDREQ[1] nXDACK[1] DMA Service Figure 7-3. Handshake Mode Diagram 7-4 S3C44B0X RISC MICROPROCESSOR DMA Single Step Mode The single step mode means that there are two DMA acknowledge cycles indicating DMA read and write cycle. The single step mode is usually used for test or debugging because the bus mastership can be handed over to other bus master between Read and Write. During the inactive period of nXDACK, i.e., between Read and Write cycle, the bus controller re-evaluates the bus priority to determine the new bus mastership. Therefore, data transfer slower than that of the hand shake mode is expected. When the DMA request signal goes low, the bus controller indicates the bus allocation for the DMA operation by lowering the DMA acknowledge signal if there is no higher priority bus request. During the first low level period of the DMA acknowledge signal, there will be a DMA read cycle. After the DMA read cycle, there will be a rising of the DMA acknowledge signal to indicate the end of the DMA read cycle. Simultaneously, the next DMA write cycle initiates if the DMA request signal is still low at the rising edge of DMA acknowledge. But, if the DMA request signal is already high at the rising edge of DMA acknowledge, the next DMA write cycle will be delayed until a new DMA request signal is activated. These two cases are shown in below Figure 7-4 and Figure 7-5. nXDREQ[1] nXDACK[1] Ready DMA Read Cycle DMA Write Cycle Figure 7-4. Single Step Mode (Case 1) nXDREQ[1] nXDACK[1] Ready State DMA Read Cycle DMA Write Cycle Idle State Figure 7-5. Single Step Mode (Case 2) 7-5 DMA S3C44B0X RISC MICROPROCESSOR Whole Service Mode The whole service mode means that the specified number of DMA operations, i.e., number of DMA operations based on transfer count, will be initiated by a single activation of DMA Request, and will be proceeded without further activations of DMA requests. The figure below shows how the whole service mode proceeds. The nXDACK signal will be active until the end of the whole DMA operations. If the number of DMA transfer operation is too large, the long bus occupation during the whole service mode of DMA operation may cause problem because the other bus services will not be provided. To solve this kind of problem, the DMA releases the bus mastership in the whole service mode every time one unit (1byte, or 1 half-word, or 1 word) is transferred. When the DMA releases the bus mastership, the other bus masters, such as the CPU, the other DMA, and the external bus master, may have bus mastership. This feature in the whole service mode can provide the optimal bus sharing, preventing the monopoly of bus mastership by DMA. If the other master intercepts the bus mastership as shown in Figure 7-7, the remainder of DMA operation can be executed after servicing the impinged bus mastership, without the re-activation of nXDREQ. nXDREQ[1] nXDACK[1] DMA Service DMA Service DMA Service Figure 7-6. Whole Service Mode nXDREQ[1] nXDACK[1] DMA Service DMA Service DMA Service The other service DMA Service DMA Service Figure 7-7. Whole Service Mode When Another Bus Master Acquires Bus Mastership 7-6 S3C44B0X RISC MICROPROCESSOR DMA Demand Mode Demand mode implies continuous DMA transfer cycles as long as DMA request signal is activated, as shown in figure 7-8. Unlike the whole service mode, this mode does not permit the bus hand-over bus mastership to higher priority bus master, which make this request to bus controller during DMA operations. In other words, no other bus master can have bus mastership during the demand mode. The sole monopoly of the bus mastership in demand mode prevents the demand mode from exceeding the specified maximum time, such as the DRAM refresh period. nXDREQ[1] nXDACK[1] DMA Service DMA Service DMA Service Figure 7-8. Demand Mode NOTE The bus controller does not permit the hand-over of bus mastership during the DMA operation using the demand mode. In other words, the DMA monopolizes bus usage right up to the completion of DMA operation. Care is warranted when using the DMA operation in the demand mode because this kind of monopoly may cause an un-expected malfunction on other masters by blocking optimal bus sharing. 7-7 DMA S3C44B0X RISC MICROPROCESSOR DMA TRANSFER MODE There are three types of DMA transfer modes (Unit transfer mode, Block transfer mode and On the fly transfer mode). Different from the external DMA request/acknowledge protocol, the DMA transfer mode defines the number of reads/writes per unit transfer as shown in the following table. DMA Transfer Mode Unit transfer Block transfer On-the-fly transfer Unit Transfer Mode The unit transfer mode means that the paired DMA read/write cycle happens corresponding each DMA request as shown below in Figure. Figure 7-9 shows the example case of the unit transfer mode at the handshake mode. Read/Write 1 unit read, then 1 unit write 4 unit burst read, then 4 unit burst write 1 unit read or 1 unit write exclusively nXDREQ[1] nXDACK[1] Read Byte Write Byte Read Byte Write Byte Figure 7-9. Unitary Transfer Mode with Handshake mode 7-8 S3C44B0X RISC MICROPROCESSOR DMA Block (4-word) Transfer Mode The block (4-word) transfer mode means that the successive 4-word DMA read cycle happens before the successive 4-word DMA write cycle, as shown in Figure 7-10. Figure 7-10 shows an example of the block transfer mode with single step mode. If the block transfer mode is used, the total data size to be transferred should be a multiple of 16 bytes. In other words, the minimum transfer size is 16 bytes, i.e., 4 words. Because the DMA count is defined in byte unit, 16 should be the DMA transfer count in the case of 4 words transfer. If the transfer size or DMA count is not a multiple of 16, for example 16, 32, 48, 64, and so on, the DMA can not transfer the data completely. If assume 100 bytestransfer (DMA count is 100), 6x16 = 96 bytes can be transferred. But, the remaining 4 bytes can not be transferred because DMA operation will be stopped after 96 bytes transfer. The users should be aware of this characteristics when they select the block transfer mode of DMA. NOTE: The ADDR[3:0] should be '0' to meet 16-byte align condition in Block Transfer Mode. nXDREQ[1] nXDACK[1] Read Burst Ready Write Burst Figure 7-10. Block Transfer Mode With Single Step Mode 7-9 DMA S3C44B0X RISC MICROPROCESSOR On-the-fly Transfer Mode The on-the-fly transfer mode means that when DMA reads/writes data, a fixed addressed external device writes/reads the data by DMA acknowledge signals (nXDACK0/1). In the other modes, the DMA reads data before writing the data. In on-the-fly transfer mode, the read and write operation occur simultaneously. The DMA acknowledge signal notifies the external device to read or write. Simultaneously, the memory controller should generate Read-related or Writerelated control signals to the external memory. If the external device can support the on-the-fly mode (can read/write the data by DMA acknowledge), the data transfer rates will be doubled. During the on-the-fly transfer cycle, S3C44B0X data bus will be in Hi-z state. Figure 7-11 shows the example of the on-the-fly transfer mode with the whole service mode. nXDREQ[1] nXDACK[1] Read Read Read Read Read Read The other service Figure 7-11. On-the-fly Transfer Mode with Whole Transfer Mode 7-10 S3C44B0X RISC MICROPROCESSOR DMA DMA REQUEST SOURCE SELECTION In ZDMA, S/W or H/W produces the nXDREQ (external DMA request signal), which is the DMA request source. The S/W trigger can be done by writing the CMD field as 01 in ZDCON0/1 register, i.e., the start of DMA. Before the start of DMA, the DMA-related parameters, such as source address, destination address, transfer count and so on, should be configured. Based-on these configuration, the DMA operation will start when the CMD field is written as 01. In S/W trigger, the DMA operations will continue as long as the burst mastership is allocated to the DMA master and as long as the DMA transfer count or TC(Terminal Count) reaches zero, i.e., the completion of DMA operation. If the higher bus master acquires the bus mastership, DMA operations will continue after the service of higher priority bus master. The DMA operations can also be initiated by nXDREQ(External DMA request signal) as well as S/W if the DMA is configured for the external trigger mode, i.e., enable External DMA request by writing QDS bit as 1 in the ZDCON0/1 register. In BDMA, there are six hardware request sources, UART0, UART1, SIO , Timer and IIS. The BDMA can be initiated by software as the ZDMA. These sources can be selected by writing the QSC field in the BDICNT register. AUTO RELOAD MODE In the auto reload mode, the register content of Z(B)DCSRCn, Z(B)DCDSTn, and Z(B)DCCNTn are reloaded from the registers of Z(B)DISRCn, Z(B)DIDESn, and Z(B)DICNTn when the DMA count decreases to 0. The configuration parameters relating to DMA operation are contained in the registers of Z(B)DISRCn, Z(B)DIDESn, and Z(B)DICNTn, for example, soure/destination address and source/destination transfer count. This kind of Auto-reloading can preschedule DMA operation automatically. In other words, to change the configuration, the configuration in the registers of Z(B)DISRCn, Z(B)DIDESn, and Z(B)DICNTn should be changed before the end of DMA operation basedon current configuration. But, this kind of parameter auto-reloading can not guarantee the DMA re-run automatically after the current DMA operation. The DMA will re-run if Z(B)DCONn CMD field is written newly or external DMA request is issued. To support the Auto-reload mdoe, the DMA should have two registers sets. The registers, Z(B)DISRCn, Z(B)DIDESn, and Z(B)DICNTn, have the initial configuration for DMA operation as above-mentioned and registers, Z(B)DCSRCn, Z(B)DCDESn and Z(B)DCCNTn, have the configuraion reflecting the current DMA operation. For example, these register should have dynamic values of source address, destination address, and the remained transfer count or TC(Terminal Count) during DMA operation. The register contents of Z(B)DISRCn, Z(B)DIDESn, and Z(B)DICNTn can be reloaded into the registers Z(B)DCSRCn, Z(B)DCDESn and Z(B)DCCNTn under one of the four cases. case 1) Auto Reload(AR) is equal to 1 and DMA Count reaches to 0, which are normal auto-reload mode of DMA operation. case 2) Writes new configuration into the Z(B)DISRC0, Z(B)DIDES0, and Z(B)DICNT0. If DMA is in Auto-reload mode, these new contests of the register will be re-loaded automatically as same as above case. If DMA is not active, these new configuration will be written into registers, Z(B)DISRC0, Z(B)DIDES0, and Z(B)DICNT0, immediately case 3) When DMA is enable, i.e., EN bit in Z(B)DICNT register changes from 0 to 1. The register contents of Z(B)DISRC0, Z(B)DIDES0, and Z(B)DICNT0 will be loaded into the registers of Z(B)DCSRC0, Z(B)DCDES0, and Z(B)DCCNT0 immediately to start of DMA operation, regardless of whether the DMA is in Auto-reload mode, or not. case 4) S/W command is Cancel. When user writes the CMD field as 11 in the register of ZDCON0/1. In this case, the register content of Z(B)DISRC0, Z(B)DIDES0, and Z(B)DICNT0 will be loaded into the registers, Z(B)DCSRC0, Z(B)DCDES0, and Z(B)DCCNT0 immediately. 7-11 DMA S3C44B0X RISC MICROPROCESSOR DMA SPECIAL REGISTERS ZDMA CONTROL REGISTER (ZDCONn) Register ZDCON0 ZDCON1 Address 0x01E80000 0x01E80020 R/W R/W R/W Description ZDMA 0 Control Register ZDMA 1 Control Register Reset Value 0x00 0x00 ZDCONn INT STE Bit [7:6] [5:4] Reserved Description Initial State 00 00 Status of DMA channel (Read only) 00 = Ready 01 = Not TC yet 10 = Terminal Count 11 = N/A Before the DMA counter decreases from the initial counter value, STE is still in the ready state. Disable/Enable External DMA request (nXDREQ) 00 = Enable other = Disable Software commands 00: No command. After writing 01,10,11, CMD bit is cleared automatically. nXDREQ is available. 01: Starts DMA operation by S/W without nXDREQ. S/W start function can be used only in the whole mode. As DMA is in the whole mode, the DMA will operate until the counter is 0. If nXDREQ is used , this command must not be issued. 10: Pauses DMA operation. But nXDREQ is still available. 11: Cancels DMA operation. QDS CMD [3:2] [1:0] 00 00 NOTE: If users start the ZDMA operation by CMD=01b, the DREQ protocol must be whole service mode. 7-12 S3C44B0X RISC MICROPROCESSOR DMA ZDMA0 INITIAL SOURCE/DESTINATION ADDRESS AND COUNT REGISTERS (ZDISRC0, ZDIDES0, ZDICNT0) Register ZDISRC0 ZDIDES0 ZDICNT0 Address 0x01E80004 0x01E80008 0x01E8000C R/W R/W R/W R/W Description ZDMA 0 initial source address Register ZDMA 0 initial destination address Register ZDMA 0 initial count register Reset Value 0x00000000 0x00000000 0x00000000 ZDMA0 CURRENT SRC/DST ADDRESS AND COUNT REGISTERS (ZDCSRC0, ZDCDES0, ZDCCNT0) Register ZDCSRC0 ZDCDES0 ZDCCNT0 NOTE: Address 0x01E80010 0x01E80014 0x01E80018 R/W R R R Description ZDMA 0 current source address Register ZDMA 0 current destination address Register ZDMA 0 current count register Reset Value 0x00000000 0x00000000 0x00000000 These registers are read-only. ZDMA1 INITIAL SOURCE/DESTINATION ADDRESS AND COUNT REGISTERS (ZDISRC1, ZDIDES1, ZDICNT1) Register ZDISRC1 ZDIDES1 ZDICNT1 Address 0x01E80024 0x01E80028 0x01E8002C R/W R/W R/W R/W Description ZDMA 1 initial source address Register ZDMA 1 initial destination address Register ZDMA 1 initial count register Reset Value 0x00000000 0x00000000 0x00000000 ZDMA1 CURRENT SRC/DST ADDRESS AND COUNT REGISTERS (ZDCSRC1, ZDCDES1, ZDCCNT1) Register ZDCSRC1 ZDCDES1 ZDCCNT1 NOTE: Address 0x01E80030 0x01E80034 0x01E80038 R/W R R R Description ZDMA 1 current source address Register ZDMA 1 current destination address Register ZDMA 1 current count register Reset Value 0x00000000 0x00000000 0x00000000 These registers are read-only. 7-13 DMA S3C44B0X RISC MICROPROCESSOR ZDMAn INITIAL/CURRENT SOURCE ADDRESS REGISTERS (ZDISRC, ZDCSRC) ZDISRCn/ZDCSRCn DST Bit [31:30] Description Data size for transfer 00 = Byte, 01 = Half word 10 = Word, 11 = Not used If the block transfer mode is used, the DST must be 10. Direction of address for load 00 = N/A, 01 = Increment 10 = Decrement, 11 = Fixed Initial/current source address for ZDMAn Initial State 00 DAL [29:28] 00 ISADDR/CSADDR [27:0] 0x0000000 ZDMAn INITIAL/CURRENT DESTINATION ADDRESS REGISTERS (ZDIDES, ZDCDE) ZDIDESn/ZDCDESn OPT Bit [31:30] Description DMA internal options. OPT = 10 is recommended. bit 31: Indicates how nXDREQ is sampled in the single step mode. 1 is recommended. bit 30: If the DST is half-word or word and if the DMA mode is not the block transfer mode, this bit takes a role. 1: DMA does word-swap or half-word swap Before transfer: B0,B1,B2,B3,B4,B5,B6,B7... word-swapped data: B3,B2,B1,B0,B7,B6,B5,B4,... half-word-swapped data: B1,B0,B3,B2,B5,B4,B7,B6,... 0: normal DAS [29:28] Direction of address for store 00 = N/A 01 = Increment 10 = Decrement 11 = Fixed Initial/current destination address for ZDMAn 00 Initial State 00 IDADDR/CDADDR [27:0] 0x0000000 7-14 S3C44B0X RISC MICROPROCESSOR DMA ZDMAn INITIAL/CURRENT COUNT REGISTERS (ZDICNT, ZDCCNT) ZDICNTn/ZDCCNTn QSC Bit [31:30] Description DREQ(DMA request) source selection 00 = nXDREQ[0] 01 = nXDREQ[1] 10 = N/A 11 = N/A DREQ protocol 00 = Handshake 10 = Whole Service 01 = Single step 11 = Demand 00 Initial State 00 QTY [29:28] 00 TMD [27:26] Transfer mode 00 = Not used 01 = Unit transfer mode 10 = Block(4-word) transfer mode 11 = On the fly If block transfer mode is selected, the ADDR[3:0] should be '0' to meet 16-byte align condition. OTF [25:24] On the fly mode 00 = N/A 10 = Read time on the fly 00 01 = N/A 11 = Write time on the fly 00 INTS [23:22] Interrupt mode set 00 = Polling mode 01 = N/A 10 = Int. whenever transferred 11 = Int. whenever terminated count Auto-reload and Auto-start after DMA count are 0. 0 = Disable 1 = Enable. Even after DMA count is 0, the DMA H/W enable bit (EN bit) is still 1. But, DMA will start to operate only if the start command or nXDREQ is activated. DMA H/W enable/disable 0 = Disable DMA 1 = Enable DMA. If the QDS bit is 00b, DMA request can be serviced. Also if the S/W command is started, the DMA operation will occur. If the EN bit is 0, DMA will not operate even though S/W command is started. If the S/W command is canceled, the DMA operation will be canceled and EN bit will be cleared to 0. At the terminal count, the EN bit will be cleared to 0. NOTE: Do not set the EN bit and the other bits of ZDICNT register at the same time. User have to set EN bit after setting the other bits of ZDICNT register as following steps, 1. Set ZDICNT register with disabled En bit. 2. Set EN bit enable. AR [21] 0 EN [20] 0 ICNT/CCNT [19:0] Initial/current transfer count for ZDMAn. If 1 byte is transferred, the ICNT will be decreased by 1. If 1 half-word is transferred, the ICNT will be decreased by 2. If 1 word is transferred, the ICNT will be decreased by 4. For example, if the data size of a transfer is word and the count is 4n+3, the last 3 bytes will not be transferred. 0x00000 7-15 DMA S3C44B0X RISC MICROPROCESSOR BDMAn CONTROL REGISTER (BDCON) Register BDCON0 BDCON1 Address 0x01F80000 0x01F80020 R/W R/W R/W Description Bridge DMA 0 Control Register Bridge DMA 1 Control Register Reset Value 0x00 0x00 BDCONn INT STE Bit [7:6] [5:4] Reserved Description Initial State 00 00 Status of DMA channel (Read only) 00 = Ready 01 = Not TC yet 10 = Terminal Count 11 = N/A Before the DMA counter decreases from a initial counter value, STE is still the ready state. Disable/Enable External/Internal DMA request (UARTn, SIO, IIS, Timer) 00 = Enable Other = Disable Software commands 00: No command. After writing 01, 10, 11, CMD bits are cleared automatically. 01: Reserved 10: Reserved 11: Cancels DMA operation. QDS [3:2] 00 CMD [1:0] 00 7-16 S3C44B0X RISC MICROPROCESSOR DMA BDMA0 INITIAL SRC/DST ADDRESS AND COUNT REGISTERS (BDISRC0, BDIDES0, BDICNT0) Register BDISRC0 BDIDES0 BDICNT0 Address 0x01F80004 0x01F80008 0x01F8000C R/W R/W R/W R/W Description BDMA 0 initial source address Register BDMA 0 initial destination address Register BDMA 0 initial count register Reset Value 0x00000000 0x00000000 0x00000000 BDMA0 CURRENT SRC/DST ADDRESS AND COUNT REGISTERS (BDCSRC0, BDCDES0, BDCCNT0) Register BDCSRC0 BDCDES0 BDCCNT0 NOTE: Address 0x01F80010 0x01F80014 0x01F80018 R/W R R R Description BDMA 0 current source address Register BDMA 0 current destination address Register BDMA 0 current count register Reset Value 0x00000000 0x00000000 0x00000000 These registers are read-only. BDMA1 INITIAL SRC/DST ADDRESS AND COUNT REGISTERS (BDISRC1, BDIDES1, BDICNT1) Register BDISRC1 BDIDES1 BDICNT1 Address 0x01F80024 0x01F80028 0x01F8002C R/W R/W R/W R/W Description BDMA 1 initial source address Register BDMA 1 initial destination address Register BDMA 1 initial count register Reset Value 0x00000000 0x00000000 0x00000000 BDMA1 CURRENT SRC/DST ADDRESS AND COUNT REGISTERS (BDCSRC1, BDCDES1, BDCCNT1) Register BDCSRC1 BDCDES1 BDCCNT1 NOTE: Address 0x01F80030 0x01F80034 0x01F80038 R/W R R R Description BDMA 1 current source address Register BDMA 1 current destination address Register BDMA 1 current count register Reset Value 0x00000000 0x00000000 0x00000000 These registers are read-only. 7-17 DMA S3C44B0X RISC MICROPROCESSOR BDMAn INITIAL/CURRENT SOURCE ADDRESS REGISTERS (BDISRC, BDCSRC) BDISRCn/BDCSRCn DST Bit [31:30] Description Data size for transfer 00 = Byte 01 = Half word 10 = Word 11 = Not used Direction of address for load 00 = N/A 01 = Increment 10 = Decrement 11 = Internal peripheral (fixed address) Initial/current source address for BDMAn. If the destination is the internal peripherals, the SFR address has to be used. For example, if the source is the UART0 Rx buffer, the UART0 Rx buffer address will be used. Initial State 00 DAL [29:28] 00 ISADDR/CSADDR [27:0] 0x0000000 BDMAn INITIAL/CURRENT DESTINATION ADDRESS REGISTERS (BDIDES, BDCDES) BDIDESn/BDCDESn TDM Bit [31:30] Description Transfer direction mode 00 = Reserved 01 = M2IO (from external memory to internal peripheral) 10 = IO2M (from internal peripheral to external memory) 11 = IO2IO (from internal peripheral to internal peripheral) NOTE: The initial value is '00' , but you must change TDM value as another though the BDMA channel is unused. Initial State 00 DAS [29:28] Direction of address for store 00 = N/A 01 = Increment 10 = Decrement 11 = Internal peripheral (fixed address) Initial/current destination address for BDMAn If the destination is the internal peripherals, the SFR address has to be used. For example, if the destination is UART0 Tx buffer, the UART0 Tx buffer address will be used. 00 IDADDR/CDADDR [27:0] 0x0000000 7-18 S3C44B0X RISC MICROPROCESSOR DMA BDMA0 INITIAL/CURRENT COUNT REGISTERS (BDICNT0, BDCCNT0) BDICNT0/BDCCNT0 QSC Bit [31:30] Description DMA request source selection 00 = N/A 01 = IIS 10 = UART0 11 = SIO 00: handshake mode 01: unit transfer mode 00: on-the-fly mode is not supported in BDMAn Interrupt mode set 00 = Polling mode 01 = N/A 10 = Int. whenever transferred 11 = Int. whenever terminated count Auto-reload and Auto-start after DMA count are 0. 0= Disable 1= Enable. Even after DMA count is 0, the DMA H/W enable bit (EN bit) is still 1. But, DMA will start to operate only if the start command or DMA request is activated DMA H/W enable/disable 0 = Disable DMA 1 = Enable DMA. If the QDS bit is 00b, DMA request can be serviced. Also if the S/W command is started, the DMA operation will occur. If the EN bit is 0, DMA will not operate even though S/W command is started. If the S/W command is canceled, the DMA operation will be canceled and EN bit will be cleared to 0. At the terminal count, the EN bit will be cleared to 0. NOTE: Do not set the EN bit and the other bits of BDICNT register at the same time. User have to set EN bit after setting the other bits of BDICNT register as following steps, 1. Set BDICNT register with disabled En bit. 2. Set EN bit enable. Initial State 00 Reserved Reserved Reserved INTS [29:28] [27:26] [25:24] [23:22] 00 01 00 00 AR [21] 0 EN [20] 0 ICNT/CCNT [19:0] Transfer count for BDMA0. The transfer count must be right value. For example, if DST is word, ICNT must be 4n. If 1 byte is transferred, the ICNT will be decreased by 1. If 1 half-word is transferred, the ICNT will be decreased by 2. If 1 word is transferred, the ICNT will be decreased by 4. 0x00000 7-19 DMA S3C44B0X RISC MICROPROCESSOR BDMA1 INITIAL/CURRENT COUNT REGISTERS (BDICNT1, BDCCNT1) BDICNT1/BDCCNT1 QSC Bit [31:30] Description DMA request source selection 00 = N/A 01 = Timer 10 = UART1 11 = SIO 00: handshake mode 01: unit transfer mode 00: on-the-fly mode is not supported in BDMAn Interrupt mode set 00 = Polling mode 01 = N/A 10 = Int. whenever transferred 11 = Int. whenever terminated count Auto-reload and Auto-start after DMA count are 0. 0= Disable 1= Enable. Even after DMA count is 0, the DMA H/W enable bit (EN bit) is still 1. But, DMA will start to operate only if the start command or DMA request is activated DMA H/W enable/disable 0 = Disable DMA 1 = Enable DMA. If the QDS bit is 00b, DMA request can be serviced. Also if the S/W command is started, the DMA operation will occur. If the EN bit is 0, DMA will not operate even though S/W command is started. If the S/W command is canceled, the DMA operation will be canceled and EN bit will be cleared to 0. At the terminal count, the EN bit will be cleared to 0. NOTE: Do not set the EN bit and the other bits of BDICNT register at the same time. User have to set EN bit after setting the other bits of BDICNT register as following steps, 1. Set BDICNT register with disabled En bit. 2. Set EN bit enable. Initial State 00 Reserved Reserved Reserved INTS [29:28] [27:26] [25:24] [23:22] 00 01 00 00 AR [21] 0 EN [20] 0 ICNT/CCNT [19:0] Transfer count for BDMA1. The transfer count must be right value. For example, if DST is word, ICNT must be 4n. If 1 byte is transferred, the ICNT will be decreased by 1. If 1 half-word is transferred, the ICNT will be decreased by 2. If 1 word is transferred, the ICNT will be decreased by 4. 0x00000 7-20 S3C44B0X RISC MICROPROCESSOR I/O PORTS 8 -- -- -- -- -- I/O PORTS OVERVIEW S3C44B0X has 71 multi-functional input/output port pins. There are seven ports: Two 9-bit input/output ports. (Port E and F) Two 8-bit input/output ports. (Port D and G) One 16-bit input/output port. (Port C) One 10-bit output port. (Port A) One 11-bit output port. (Port B) Each port can be easily configured by software to meet various system configuration and design requirements. The function of each pin to be used must be defined before starting the main program. If the multiplexed functions on a pin are not used, the pin can be configured as I/O ports. Before pin configurations, the initial pin states are configured elegantly to avoid some problems. 8-1 I/O PORTS S3C44B0X RISC MICROPROCESSOR Table 8-1. S3C44B0X Port Configuration Overview Port A Function 1 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 output only output only output only output only output only output only output only output only output only output only Selectable Pin functions Function 2 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 Port B Function 1 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 output only output only output only output only output only output only output only output only output only output only output only Selectable Pin functions Function 2 nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 nWBE3:nBE3:DQM3 nWBE2:nBE2:DQM2 nSRAS:nCAS3 nSCAS:nCAS2 SCLK SCKE 8-2 S3C44B0X RISC MICROPROCESSOR I/O PORTS Table 8-1. S3C44B0X Port Configuration Overview (Continued) Port C Function 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin functions Function 2 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 Function 3 nCTS0 nRTS0 RxD1 TxD1 nCTS1 nRTS1 nXDREQ1 nXDACK1 VD4 VD5 VD6 VD7 IISCLK IISDI IISDO IISLRCK Port D Function 1 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin functions Function 2 VFRAME VM VLINE VCLK VD3 VD2 VD1 VD0 8-3 I/O PORTS S3C44B0X RISC MICROPROCESSOR Table 8-1. S3C44B0X Port Configuration Overview (Continued) Port E Function 1 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 ENDIAN Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin functions Function 2 CODECLK TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 RxD0 TxD0 Fpllo Function 3 input/output VD7 VD6 TCLK TCLK Fout Port F Function 1 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 input/output input/output input/output input/output input/output input/output input/output input/output input/output Selectable Pin functions Function 2 nCTS1 RxD1 TxD1 nRTS1 nXBREQ nXBACK nWAIT IICSDA IICSCL Function 3 SIOCK SIORxD SIORDY SIOTxD nXDREQ0 nXDACK0 - - - Function 4 IISCLK IISDI IISDO IISLRCK - - - - - Port G Function 1 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 NOTES: Selectable Pin Functions Function 2 IISLRCK IISDO IISDI IISCLK nRTS0 nCTS0 VD5 VD4 Function 3 EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 input/output input/output input/output input/output input/output input/output input/output input/output 8-4 S3C44B0X RISC MICROPROCESSOR I/O PORTS 1. 2. The underlined function name is selected just after a reset.(ENDIAN(PE8) is used only when nRESET is L. IICSDA and IICSCL pins are open-drain pin. So, this pin needs pull-up resistors when used as output port(PF[1:0]). PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (PCONA-G) In S3C44B0X, most pins are multiplexed pins. Therefore, the functions for each pin should be selected. The PCONn (port control register) determines which function is used for each pin. If PG0 - PG7 are used for the wakeup signal in power down mode, these ports must be configured in interrupt mode. PORT DATA REGISTER (PDATA-G) If these ports are configured as output ports, data can be written to the corresponding bit of PDATn. If Ports are configured as input ports, the data can be read from the corresponding bit of PDATn. PORT PULL-UP REGISTER (PUPC-G) The port pull-up resistor controls the pull-up resistor enable/disable of each port group. When the corresponding bit is 0, the pull-up resistor of the pin is enabled. When 1, the pull-up resistor is disabled. EXTERNAL INTERRUPT CONTROL REGISTER The 8 external interrupts are requested by various signaling methods. The EXTINT register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge triggers for the external interrupt request Because each external interrupt pin has a digital filter, the interrupt controller can recognize the request signal longer than 3 clocks. 8-5 I/O PORTS S3C44B0X RISC MICROPROCESSOR I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS (PCONA, PDATA, PUPA) Port A control registers are shown in Table 8-2: Register PCONA PDATA Address 0x01D20000 0x01D20004 R/W R/W R/W Description Configures the pins of port A The data register for port A Reset Value 0x3ff Undef. Table 8-2. Port of Group A Control Registers (PCONA,PDATA) PCONA PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Bit [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output Description 1 = ADDR24 1 = ADDR23 1 = ADDR22 1 = ADDR21 1 = ADDR20 1 = ADDR19 1 = ADDR18 1 = ADDR17 1 = ADDR16 1 = ADDR0 PDATA PA[9:0] Bit [9:0] Description When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, an undefined value will be read. 8-6 S3C44B0X RISC MICROPROCESSOR I/O PORTS PORT B CONTROL REGISTERS (PCONB, PDATB) Port B control registers are shown in Table 8-3: Register PCONB PDATB Address 0x01D20008 0x01D2000C R/W R/W R/W Description Configures the pins of port B The data register for port B Reset Value 0x7ff Undef. Table 8-3. Port of Group B Control Registers (PCONB,PDATB) PCONB PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Bit [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output Description 1 = nGCS5 1 = nGCS4 1 = nGCS3 1 = nGCS2 1 = nGCS1 1 = nWBE3/nBE3/DQM3 1 = nWBE2/nBE2/DQM2 1 = nSRAS/nCAS3 1 = nSCAS/nCAS2 1 = SCLK 1 = SCKE PDATB PB[10:0] Bit [10:0] Description When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, an undefined value will be read. 8-7 I/O PORTS S3C44B0X RISC MICROPROCESSOR PORT C CONTROL REGISTERS (PCONC, PDATC, PUPC) Port C control registers are shown in Table 8-4: Register PCONC PDATC PUPC Address 0x01D20010 0x01D20014 0x01D20018 R/W R/W R/W R/W Description Configures the pins of port C The data register for port C pull-up disable register for port C Reset Value 0xaaaaaaaa Undef. 0x0 Table 8-4. Port of Group C Control Registers (PCONC,PDATC,PUPC) PCONC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = DATA31 00 = Input 10 = DATA30 00 = Input 10 = DATA29 00 = Input 10 = DATA28 00 = Input 10 = DATA27 00 = Input 10 = DATA26 00 = Input 10 = DATA25 00 = Input 10 = DATA24 00 = Input 10 = DATA23 00 = Input 10 = DATA22 00 = Input 10 = DATA21 00 = Input 10 = DATA20 00 = Input 10 = DATA19 00 = Input 10 = DATA18 00 = Input 10 = DATA17 00 = Input 10 = DATA16 01 = Output 11 = nCTS0 01 = Output 11 = nRTS0 01 = Output 11 = RxD1 01 = Output 11 = TxD1 01 = Output 11 = nCTS1 01 = Output 11 = nRTS1 01 = Output 11 = nXDREQ1 01 = Output 11 = nXDACK1 01 = Output 11 = VD4 01 = Output 11 = VD5 01 = Output 11 = VD6 01 = Output 11 = VD7 01 = Output 11 = IISCLK 01 = Output 11 = IISDI 01 = Output 11 = IISDO 01 = Output 11 = IISLRCK Description 8-8 S3C44B0X RISC MICROPROCESSOR I/O PORTS PDATC PC[15:0] Bit [15:0] Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, an undefined value will be read. PUPC PC[15:0] Bit [15:0] Description 0: the pull up resistor attached to the corresponding port pin is enabled. 1: the pull up resistor is disabled. 8-9 I/O PORTS S3C44B0X RISC MICROPROCESSOR PORT D CONTROL REGISTERS (PCOND, PDATD, PUPD) Port D control registers are shown in Table 8-5. Register PCOND PDATD PUPD Address 0x01D2001C 0x01D20020 0x01D20024 R/W R/W R/W R/W Description Configures the pins of port D The data register for port D Pull-up disable register for port D Reset Value 0x0000 Undef. 0x0 Table 8-5. Port of Group D Control Registers (PCOND, PDATD, PUPD) PCOND PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Bit [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = VFRAME 00 = Input 10 = VM 00 = Input 10 = VLINE 00 = Input 10 = VCLK 00 = Input 10 = VD3 00 = Input 10 = VD2 00 = Input 10 = VD1 00 = Input 10 = VD0 Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved PDATD PD[7:0] Bit [7:0] Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, an undefined value will be read. PUPD PD[7:0] Bit [7:0] Description 0: the pull up resistor attached to the corresponding port pin is enabled. 1: the pull up resistor is disabled. 8-10 S3C44B0X RISC MICROPROCESSOR I/O PORTS PORT E CONTROL REGISTERS (PCONE, PDATE) Port E control registers are shown in Table 8-6: Register PCONE PDATE PUPE Address 0x01D20028 0x01D2002C 0x01D20030 R/W R/W R/W R/W Description Configures the pins of port E The data register for port E pull-up disable register for port E Reset Value 0x00 Undef. 0x00 Table 8-6. Port of Group E Control Registers (PCONE, PDATE) PCONE PE8 Bit [17:16] Description 00 = Reserved(ENDIAN) 01 = Output 10 = CODECLK 11 = Reserved PE8 can be used as ENDIAN only during the reset cycle. 00 = Input 10 = TOUT4 00 = Input 10 = TOUT3 00 = Input 10 = TOUT2 00 = Input 10 = TOUT1 00 = Input 10 = TOUT0 00 = Input 10 = RxD0 00 = Input 10 = TxD0 00 = Input 10 = Fpllo out 01 = Output 11 = VD7 01 = Output 11 = VD6 01 = Output 11 = TCLK in 01 = Output 11 = TCLK in 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Fout out PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 NOTE: [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] Please refer to Fig. 5-1 when selecting Fpllo or Fout. PDATE PE[8:0] Bit [8:0] Description When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read. PUPE PE[7:0] Bit [7:0] Description 0: the pull up resistor attached to the corresponding port pin is enabled. 1: the pull up resistor is disabled. PE8 do not have programmable pull-up resistor. 8-11 I/O PORTS S3C44B0X RISC MICROPROCESSOR PORT F CONTROL REGISTERS (PCONF, PDATF, PUPF) Port F control registers are shown in Table 8-7 below: Register PCONF PDATF PUPF Address 0x01D20034 0x01D20038 0x01D2003C R/W R/W R/W R/W Description Configures the pins of port F The data register for port F pull-up disable register for port F Reset Value 0x0000 Undef. 0x000 Table 8-7. Port of Group F Control Registers (PCONF, PDATF, PUPF) PCONF PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Bit [21:19] [18:16] [15:13] [12:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000 = Input 011 = SIOCLK 000 = Input 011 = SIORxD 000 = Input 011 = SIORDY 000 = Input 011 = SIOTxD 00 = Input 10 = nXBREQ 00 = Input 10 = nXBACK 00 = Input 10 = nWAIT 00 = Input 10 = IICSDA 00 = Input 10 = IICSCL 001 = Output 100 = IISCLK 001 = Output 100 = IISDI 001 = Output 100 = IISDO 001 = Output 100 = IISLRCK Description 010 = nCTS1 Others = Reserved 010 = RxD1 Others = Reserved 010 = TxD1 Others = Reserved 010 = nRTS1 Others = Reserved 01 = Output 11 = nXDREQ0 01 = Output 11 = nXDACK0 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved PDATF PF[8:0] Bit [8:0] Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read. PUPF PF[8:0] Bit [8:0] Description 0: the pull up resistor attached to the corresponding port pin is enabled. 1: the pull up resistor is disabled. 8-12 S3C44B0X RISC MICROPROCESSOR I/O PORTS PORT G CONTROL REGISTERS (PCONG, PDATG, PUPG) Port G control registers are shown in Table 8-8: If PG0 - PG7 are to be used for wake-up signals in power down mode, the ports will be set in the interrupt mode. Register PCONG PDATG PUPG Address 0x01D20040 0x01D20044 0x01D20048 R/W R/W R/W R/W Description Configures the pins of port G The data register for port G Pull-up disable register for port G Reset Value 0x0 Undef. 0x0 Table 8-8. Port of Group G Control Registers (PCONG, PDATG, PUPG) PCONG PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Bit [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = IISLRCK 00 = Input 10 = IISDO 00 = Input 10 = IISDI 00 = Input 10 = IISCLK 00 = Input 10 = nRTS0 00 = Input 10 = nCTS0 00 = Input 10 = VD5 00 = Input 10 = VD4 Description 01 = Output 11 = EINT7 01 = Output 11 = EINT6 01 = Output 11 = EINT5 01 = Output 11 = EINT4 01 = Output 11 = EINT3 01 = Output 11 = EINT2 01 = Output 11 = EINT1 01 = Output 11 = EINT0 PDATG PG[7:0] Bit [7:0] Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read. PUPG PG[7:0] Bit [7:0] Description 0: the pull up resistor attached to the corresponding port pin is enabled. 1: the pull up resistor is disabled. 8-13 I/O PORTS S3C44B0X RISC MICROPROCESSOR SPECIAL PULL-UP RESISTOR CONTROL REGISTER (SPUCR) D[15:0] pin pull-up resistor can be controlled by the SPUCR register. In STOP/SL_IDLE mode, the data bus(D[31:0] or D[15:0] is in Hi-Z state. But, because of the characteristics of IO pad, the data bus pull-up resistors have to be turned on to reduce the power consumption in STOP/SL_IDLE mode. D[31:16] pin pull-up resistors can be controlled by PUPC register. D[15:0] pin pull-up resistors can be controlled by the SPUCR register. In STOP mode, memory control signals can be selected as Hi-z state or previous state in order to protect against memory mal-functions by setting the HZ@STOP field in SPUCR register. Register SPUCR Address 0x01D2004C R/W R/W Description Special Pull-up register[2:0] Reset Value 0x4 Table 8-9. D[15:0] Pull-up Control Register (SPUCR) PCONG HZ@STOP SPUCR1 SPUCR0 Bit [2] [1] [0] 0 = Previous state of PAD Description 1 = HZ @ stop 0 = DATA[15:8] port pull-up resistor is enabled 1 = DATA[15:8] port pull-up resistor is disabled 0 = DATA[7:0] port pull-up resistor is enabled 1 = DATA[7:0] port pull-up resistor is disabled 8-14 S3C44B0X RISC MICROPROCESSOR I/O PORTS EXTINT (EXTERNAL INTERRUPT CONTROL REGISTER) The 8 external interrupts can be requested by various signaling methods. The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. Register EXTINT Address 0x01D20050 R/W R/W Description External Interrupt control Register Reset Value 0x000000 Table 8-10. External Interrupt Control Register (EXTINT) EXTINT EINT7 Bit [30:28] Description Setting the signaling method of the EINT7. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT6. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT5. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT4. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT3. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT2. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT1. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Setting the signaling method of the EINT0. 000 = Low level interrupt 001 = High level interrupt 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered EINT6 [26:24] EINT5 [22:20] EINT4 [18:16] EINT3 [14:12] EINT2 [10:8] EINT1 [6:4] EINT0 [2:0] NOTE: Because each external interrupt pin has a digital filter, the interrupt controller can recognize a request signal that is longer than 3 clocks. 8-15 I/O PORTS S3C44B0X RISC MICROPROCESSOR EXTINTPND (EXTERNAL INTERRUPT PENDING REGISTER) The external interrupt requests(4, 5, 6, and 7) are 'OR'ed to provide a single interrupt source to interrupt controller. EINT4, EINT5, EINT6, and EINT7 share the same interrupt request line(EINT4/5/6/7) in interrupt controller. If each of the 4 bits in the external interrupt request is generated, EXTINTPNDn will be set as 1. The interrupt service routine must clear the interrupt pending condition(INTPND) after clearing the external pending condition(EXTINTPND). EXTINTPND is cleared by writing 1. Register EXTINTPND Address 0x01D20054 R/W R/W Description External interrupt pending Register Reset Value 0x00 Table 8-11. D[15:0] Pull-Up Control Register (PUPS) PUPS EXTINTPND3 EXTINTPND2 EXTINTPND1 EXTINTPND0 Bit [3] [2] [1] [0] Description If EINT7 is activated, EXINTPND3 bit is set to 1, and also INTPND[21] is set to 1. If EINT6 is activated, EXINTPND2 bit is set to 1, and also INTPND[21] is set to 1. If EINT5 is activated, EXINTPND1 bit is set to 1, and also INTPND[21] is set to 1. If EINT4 is activated, EXINTPND0 bit is set to 1, and also INTPND[21] is set to 1. 8-16 S3C44B0X RISC MICROPROCESSOR PWM TIMER 9 PWM TIMER OVERVIEW The S3C44B0X has six 16-bit timers, each timer can operate in interrupt-based or DMA-based mode. The timers 0, 1, 2, 3 and 4 have the PWM function (Pulse Width Modulation). Timer 5 has an internal timer only with no output pins. Timer 0 has a dead-zone generator, which is used with a large current device. Timer 0 and timer 1 share an 8-bit prescaler; timers 2 & 3 share another 8-bit prescaler; and timers 4 & 5 share the other 8-bit prescaler. Each timer, except timers 4 and 5, has a clock-divider which has 5 different divided signals (1/2, 1/4, 1/8, 1/16, 1/32). Timers 4/5 have 4 divided signals(1/2, 1/4, 1/8, 1/16) and one input TCLK/EXTCLK. Each timer block receives its own clock signals from the clock-divider, which receives the clock from the corresponding 8bit prescaler. The 8-bit prescaler is programmable and divides the MCLK signal according to the loading value which is stored in TCFG0 and TCFG1 registers. The timer count buffer register(TCNTBn) has an initial value which is loaded into the down-counter when the timer is enabled. The timer compare buffer register(TCMPBn) has an initial value which is loaded into the compare register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed. Each timer has its own 16-bit down-counter which is driven by the timer clock. When the down-counter reaches zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down-counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter. The value of TCMPBn is used for PWM (pulse width modulation). The timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the compare register determines the turn-on time(or turn-off time) of an PWM output. FEATURES -- -- -- -- -- Six 16-bit timers with DMA-based or interrupt-based operation Three 8-bit prescalers & Two 5-bit dividers & One 4-bit divider Programmable duty control of output waveform (PWM) Auto-reload mode or one-shot pulse mode Dead-zone generator 9-1 PWM TIMER S3C44B0X RISC MICROPROCESSOR TCMPB0 TCNTB0 Dead Zone Generator MUX0 TOUT0 MUX0 Control Logic MCLK 8-Bit Prescaler 1/2 1/4 1/8 1/16 1/32 MUX1 Clock Divider Control Logic TCMPB1 TCNTB1 TOUT1 TCMPB2 TCNTB2 TOUT2 Control Logic MUX2 1/2 1/4 8-Bit Prescaler 1/8 1/16 1/32 MUX3 Clock Divider Control Logic TOUT3 TCMPB3 TCNTB3 TCMPB4 TCNTB4 TOUT4 Control Logic MUX4 1/2 8-Bit Prescaler 1/4 1/8 1/16 MUX5 Clock Divider Control Logic TOUT5 (No Pin) TCLK TCNTB5 EXTCLK Figure 9-1. 16-bit PWM Timer Block Diagram 9-2 S3C44B0X RISC MICROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and an independent 4-bit divider make the following output frequencies: 4-bit divider settings 1/2 ( MCLK = 66 MHz ) 1/4 ( MCLK = 66 MHz ) 1/8 ( MCLK = 66 MHz ) 1/16 ( MCLK = 66 MHz ) 1/32 ( MCLK = 66 MHz ) minimum resolution (prescaler = 1) 0.030 us (33.0 MHz ) 0.060 us (16.5 MHz ) 0.121 us (8.25 MHz ) 0.242 us (4.13 MHz ) 0.485 us (2.06 MHz ) maximum resolution (prescaler = 255) 7.75 us (58.6 KHz ) 15.5 us (58.6 KHz ) 31.0 us (29.3 KHz ) 62.1 us (14.6 KHz ) 125 us (7.32 KHz ) maximum interval (TCNTBn = 65535) 0.50 sec 1.02 sec 2.03 sec 4.07 sec 8.13 sec BASIC TIMER OPERATION Start bit = 1 Timer is started TCNTn = TCMPn Auto-reload TCNTn = TCMPn Timer is stopped TCMPn 1 0 TCNTn 3 3 2 1 0 2 1 0 0 Auto-reload = 0 TCNTBn = 3 TCMPBn = 1 Manual Update = 1 Auto-reload = 1 TCNTBn = 2 TCMPBn = 0 Manual Update = 0 Auto-reload = 1 Interrupt Request Interrupt Request TOUTn Command Status Figure 9-2. Timer operations A timer (except the timer ch-5) has TCNTBn, TCNTn, TCMPBn and TCMPn. TCNTBn and TCMPBn are loaded into TCNTn and TCMPn when the timer reaches 0. When TCNTn reaches 0, the interrupt request will occur if the interrupt is enabled. (TCNTn and TCMPn are the names of the internal registers. The TCNTn register can be read from the TCNTOn register) 9-3 PWM TIMER S3C44B0X RISC MICROPROCESSOR AUTO-RELOAD & DOUBLE BUFFERING S3C44B0X PWM Timers have a double buffering feature, which can change the reload value for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into TCNTBn (timer counter buffer register) and the current counter value of the timer can be read from TCNTOn (timer count observation register). If TCNTBn is read, the read value is not the current state of the counter but the reload value for the next timer duration. The auto-reload is the operation, which copies the TCNTBn into TCNTn when TCNTn reaches 0. The value, written into TCNTBn, is loaded to TCNTn only when the TCNTn reaches to 0 and auto-reload is enabled. If the TCNTn is 0 and the auto-reload bit is 0, the TCNTn does not operate any further. Write TCNTBn = 100 Start TCNTBn = 150 Write TCNTBn = 200 Auto-reload 150 100 100 200 Interrupt Figure 9-3. Example of Double Buffering Feature 9-4 S3C44B0X RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT Because an auto-reload operation of the timer occurs when the down counter reaches to 0, a starting value of the TCNTn is not defined at first. In this case, the starting value has to be loaded by the manual update bit. The sequence of starting a timer is as follows; 1) Write the initial value into TCNTBn and TCMPBn 2) Set the manual update bit of the corresponding timer. It is recommended to configure the inverter on/off bit. 3) Set the start bit of the corresponding timer to start the timer(At the same time, clear the manual update bit). Also, if the timer is stopped by force, the TCNTn retains the counter value and is not reloaded from TCNTBn. If new value has to be set, manual update has to be done. NOTE Whenever TOUT inverter on/off bit is changed, the TOUTn logic value will be changed whether or not the timer runs. Therefore, it is desirable that the inverter on/off bit is configured with the manual update bit. 9-5 PWM TIMER S3C44B0X RISC MICROPROCESSOR EXAMPLE OF A TIMER OPERATION 1 2 3 4 6 79 10 TOUTn 50 110 40 40 20 60 5 8 11 Figure 9-4. Example of a Timer Operation The result of the following procedure is shown in Figure 9-4. 1. Enable the auto-reload feature. Set the TCNTBn as 160 (50+110) and the TCMPBn as 110. Set the manual update bit and configure the inverter bit(on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively. And then, set TCNTBn and TCMPBn as 80 (40+40) and 40, respectively, to determine the next reload value. 2. 3. 4. 5. 6. 7. 8. 9. Set the start bit, provided that manual_update is 0 and inverter is off and auto-reload is on. The timer starts counting down after latency time within the timer resolution. When TCNTn has the same value with TCMPn, the logic level of TOUTn is changed from low to high. When TCNTn reaches 0, the interrupt request is generated and TCNTBn value is loaded into a temporary register. At the next timer tick, TCNTn is reloaded with the temporary register value(TCNTBn). In the ISR(interrupt service routine), the TCNTBn and TCMPBn are set as 80 (20+60) and 60, respectively, which is used for the next duration. When TCNTn has the same value as TCMPn, the logic level of TOUTn is changed from low to high. When TCNTn reaches 0, TCNTn is reloaded automatically with TCNTBn. At the same time, the interrupt request is generated. In the ISR (interrupt service routine), auto-reload and interrupt request are disabled to stop the timer. When the value of TCNTn is same as TCMPn, the logic level of TOUTn is changed from low to high. 10. Even when TCNTn reaches to 0, TCNTn is not any more reloaded and the timer is stopped because auto-reload has been disabled. 11. No interrupt request is generated. 9-6 S3C44B0X RISC MICROPROCESSOR PWM TIMER PWM (PULSE WIDTH MODULATION) 60 50 40 30 30 Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value Figure 9-5. Example of PWM PWM feature can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. A PWM value is determined by TCMPBn in figure 9-5. For a lower PWM output value, decrease the TCMPBn value. For a higher PWM output value, increase the TCMPBn value. If an output inverter is enabled, the increment/decrement may be reversed. Because of the double buffering feature, TCMPBn, for a next PWM cycle, can be written at any point in the current PWM cycle by ISR or something else 9-7 PWM TIMER S3C44B0X RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 9-6. Inverter On/Off The following methods can be used to maintain TOUT as high or low.(assume the inverter is off) 1. 2. 3. 4. Turn off the auto-reload bit. And then, TOUTn goes to high level and the timer is stopped after TCNTn reaches to 0. This method is recommended. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn TCMPn, the output level is high. If TCNTn >TCMPn, the output level is low. Write the TCMPBn which is bigger than TCNTBn. This inhibits the TOUTn from going to high because TCMPBn can not have the same value as TCNTn. TOUTn can be inverted by the inverter on/off bit in TCON. The inverter removes the additional circuit to adjust the output level. 9-8 S3C44B0X RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This feature is used to insert the time gap between a turnoff of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices turning on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0. If the dead zone is enabled, the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ, respectively. nTOUT0_DZ is routed to the TOUT1 pin. In the dead zone interval, TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously. TOUT0 nTOUT0 Deadzone Interval TOUT0_DZ nTOUT0_DZ Figure 9-7. The Wave Form When a Dead Zone Feature is Enabled 9-9 PWM TIMER S3C44B0X RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate a DMA request at every specific times. The timer keeps DMA request signal low until the timer receives the ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. One of 6 timers can generate a DMA request. The timer, that generates the DMA request, is determined by setting DMA mode bits(in TCFG1 register). If a timer is configured as DMA request mode, the timer does not generate an interrupt request. The others can generate interrupt normally. DMA mode configuration and DMA / interrupt operation DMA mode 0000 0001 0010 0011 0100 0101 0110 0111 DMA request No select Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 No select Timer0 INT ON OFF ON ON ON ON ON ON Timer1 INT ON ON OFF ON ON ON ON ON Timer2 INT ON ON ON OFF ON ON ON ON Timer3 INT ON ON ON ON OFF ON ON ON Timer4 INT ON ON ON ON ON OFF ON ON Timer5 INT ON ON ON ON ON ON OFF ON MCLK Timer4_Int_tmp DMA mode 101 nDMA_ACK nDMA_REQ Timer4_Int Figure 9-8. The Timer4 DMA mode operation 9-10 S3C44B0X RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = MCLK / {prescaler value + 1} / {divider value} {prescaler value} = 0-255 {divider value} = 2, 4, 8, 16, 32 Register TCFG0 Address 0x01D50000 R/W R/W Description Configures the three 8-bit prescalers Reset Value 0x00000000 TCFG0 Dead zone length Prescaler 2 Prescaler 1 Prescaler 0 Bit [31:24] [23:16] [15:8] [7:0] Description These 8 bits determine the dead zone length. The 1 unit time of the dead zone length is equal to the 1 unit time of timer 0. These 8 bits determine prescaler value for Timer 4 & 5 These 8 bits determine prescaler value for Timer 2 & 3 These 8 bits determine prescaler value for Timer 0 & 1 Initial State 0x00 0x00 0x00 0x00 9-11 PWM TIMER S3C44B0X RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 (TCFG1) Register TCFG1 Address 0x01D50004 R/W R/W Description 6-MUX & DMA mode selecton register Reset Value 0x00000000 TCFG1 DMA mode Bit [27:24] Description Select DMA request channel 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Timer5 0111 = Reserved Select MUX input for PWM Timer5. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = EXTCLK Select MUX input for PWM Timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = TCLK Select MUX input for PWM Timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = 1/32 Select MUX input for PWM Timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = 1/32 Select MUX input for PWM Timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = 1/32 Select MUX input for PWM Timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = 1/32 Initial State 000 MUX 5 [23:20] 000 MUX 4 [19:16] 000 MUX 3 [15:12] 000 MUX 2 [11:8] 000 MUX 1 [7:4] 000 MUX 0 [3:0] 000 9-12 S3C44B0X RISC MICROPROCESSOR PWM TIMER TIMER CONTROL REGISTER (TCON) Register TCON Address 0x01D50008 R/W R/W Description Timer control register Reset Value 0x00000000 TCON Timer 5 auto reload on/off Timer 5 manual update (note) Timer 5 start/stop Timer 4 auto reload on/off Timer 4 output inverter on/off Timer 4 manual update (note) Timer 4 start/stop Timer 3 auto reload on/off Timer 3 output inverter on/off Timer 3 manual update (note) Timer 3 start/stop Timer 2 auto reload on/off Timer 2 output inverter on/off Timer 2 manual update (note) Timer 2 start/stop NOTE: Bit [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] Description This bit determines auto reload on/off for Timer 5. 0 = One-shot 1 = Interval mode (auto reload) This bit determines the manual update for Timer 5. 0 = No operation 1 = Update TCNTB5 This bit determines start/stop for Timer 5. 0 = Stop 1 = Start for Timer 5 This bit determines auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer4. 0 = Inverter off 1 = Inverter on for TOUT4 This bit determines the manual update for Timer 4. 0 = No operation 1 = Update TCNTB4, TCMPB4 This bit determines start/stop for Timer 4. 0 = Stop 1 = Start for Timer 4 This bit determines auto reload on/off for Timer 3. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer 3. 0 = Inverter off 1 = Inverter on for TOUT3 This bit determine manual update for Timer 3. 0 = No operation 1 = Update TCNTB3, TCMPB3 This bit determines start/stop for Timer 3. 0 = Stop 1 = Start for Timer 3 This bit determines auto reload on/off for Timer 2. 0 = One-shot 1 = Interval mode (auto reload) This bit determines output inverter on/off for Timer 2. 0 = Inverter off 1 = Inverter on for TOUT2 This bit determines the manual update for Timer 2. 0 = No operation 1 = Update TCNTB2, TCMPB2 This bit determines start/stop for Timer 2. 0 = Stop 1 = Start for Timer 2 initial state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This bit has to be cleared at next writing. 9-13 PWM TIMER S3C44B0X RISC MICROPROCESSOR TIMER CONTROL REGISTER (TCON) (Continued) TCON Timer 1 auto reload on/off Timer 1 output inverter on/off Timer 1 manual update (note) Timer 1 start/stop Dead zone enable Timer 0 auto reload on/off Timer 0 output inverter on/off Timer 0 manual update (note) Timer 0 start/stop NOTE: Bit [11] [10] [9] [8] [4] [3] [2] [1] [0] Description This bit determines the auto reload on/off for Timer1. 0 = One-shot 1 = Interval mode (auto reload) This bit determines the output inverter on/off for Timer1. 0 = Inverter off 1 = Inverter on for TOUT1 This bit determines the manual update for Timer 1. 0 = No operation 1 = Update TCNTB1, TCMPB1 This bit determines start/stop for Timer 1. 0 = Stop 1 = Start for Timer 1 This bit determines the dead zone operation. 0 = Disable 1 = Enable This bit determines auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) This bit determines the output inverter on/off for Timer 0. 0 = Inverter off 1 = Inverter on for TOUT0 This bit determines the manual update for Timer 0. 0 = No operation 1 = Update TCNTB0, TCMPB0 This bit determines start/stop for Timer 0. 0 = Stop 1 = Start for Timer 0 initial state 0 0 0 0 0 0 0 0 0 This bit has to be cleared at next writing. 9-14 S3C44B0X RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0, TCMPB0) Register TCNTB0 TCMPB0 Address 0x01D5000C 0x01D50010 R/W R/W R/W Description Timer 0 count buffer register Timer 0 compare buffer register Reset Value 0x00000000 0x00000000 TCMPB0 Timer 0 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 0 NOTE: This value must be smaller than TCNTB0 Initial State 0x00000000 TCNTB0 Timer 0 count buffer register Bit [15:0] Description Setting count buffer value for Timer 0 Initial State 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER (TCNTO0) Register TCNTO0 Address 0x01D50014 R/W R Description Timer 0 count observation register Reset Value 0x00000000 TCNTO0 Timer 0 observation register Bit [15:0] Description Setting count observation value for Timer 0 Initial State 0x00000000 9-15 PWM TIMER S3C44B0X RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1, TCMPB1) Register TCNTB1 TCMPB1 Address 0x01D50018 0x01D5001C R/W R/W R/W Description Timer 1 count buffer register Timer 1 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB1 Timer 1 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 1 NOTE: This value must be smaller than TCNTB1 Initial State 0x00000000 TCNTB1 Timer 1 count buffer register Bit [15:0] Description Setting count buffer value for Timer 1 Initial State 0x00000000 TIMER 1 COUNT OBSERVATION REGISTER(TCNTO1) Register TCNTO1 Address 0x01D50020 R/W R Description Timer 1 count observation register Reset Value 0x00000000 TCNTO1 Timer 1 observation register Bit [15:0] Description Setting count observation value for Timer 1 initial state 0x00000000 9-16 S3C44B0X RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2, TCMPB2) Register TCNTB2 TCMPB2 Address 0x01D50024 0x01D50028 R/W R/W R/W Description Timer 2 count buffer register Timer 2 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB2 Timer 2 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 2 NOTE: This value must be smaller than TCNTB2 Initial State 0x00000000 TCNTB2 Timer 2 count buffer register Bit [15:0] Description Setting count buffer value for Timer 2 Initial State 0x00000000 TIMER 2 COUNT OBSERVATION REGISTER (TCNTO2) Register TCNTO2 Address 0x01D5002C R/W R Description Timer 2 count observation register Reset Value 0x00000000 TCNTO2 Timer 2 observation register Bit [15:0] Description Setting count observation value for Timer 2 Initial State 0x00000000 9-17 PWM TIMER S3C44B0X RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3, TCMPB3) Register TCNTB3 TCMPB3 Address 0x01D50030 0x01D50034 R/W R/W R/W Description Timer 3 count buffer register Timer 3 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB3 Timer 3 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 3 NOTE: This value must be smaller than TCNTB3 Initial State 0x00000000 TCNTB3 Timer 3 count buffer register Bit [15:0] Description Setting count buffer value for Timer 3 Initial State 0x00000000 TIMER 3 COUNT OBSERVATION REGISTER (TCNTO3) Register TCNTO3 Address 0x01D50038 R/W R Description Timer 3 count observation register Reset Value 0x00000000 TCNTO3 Timer 3 observation register Bit [15:0] Description Setting count observation value for Timer 3 Initial State 0x00000000 9-18 S3C44B0X RISC MICROPROCESSOR PWM TIMER TIMER 4 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB4, TCMPB4) Register TCNTB4 TCMPB4 Address 0x01D5003C 0x01D50040 R/W R/W R/W Description Timer 4 count buffer register Timer 4 campare buffer register Reset Value 0x00000000 0x00000000 TCMPB4 Timer 4 compare buffer register Bit [15:0] Description Setting compare buffer value for Timer 4 NOTE: This value must be smaller than TCNTB4 Initial State 0x00000000 TCNTB4 Timer 4 count buffer register Bit [15:0] Description Setting count buffer value for Timer 4 Initial State 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register TCNTO4 Address 0x01D50044 R/W R Description Timer 4 count observation register Reset Value 0x00000000 TCNTO4 Timer 4 observation register Bit [15:0] Description Setting count observation value for Timer 4 Initial State 0x00000000 9-19 PWM TIMER S3C44B0X RISC MICROPROCESSOR TIMER 5 COUNT BUFFER REGISTER (TCNTB5) Register TCNTB5 Address 0x01D50048 R/W R/W Description Timer 5 count buffer register Reset Value 0x00000000 TCNTB5 Timer 5 count buffer register Bit [15:0] Description Setting count buffer value for Timer 5 Initial State 0x00000000 TIMER 5 COUNT OBSERVATION REGISTER (TCNTO5) Register TCNTO5 Address 0x01D5004C R/W R Description Timer 5 count observation register Reset Value 0x00000000 TCNTO5 Timer 5 observation register Bit [15:0] Description Setting count observation value for Timer 5 Initial State 0x00000000 9-20 S3C44B0X RISC MICROPROCESSOR UART 10 OVERVIEW UART The S3C44B0X UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can support bit rates of up to 115.2K bps. Each UART channel contains two 16-byte FIFOs for receive and transmit. The S3C44B0X UART includes programmable baud-rates, infra-red (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure10-1. The baudrate generator can be clocked by MCLK. The transmitter and the receiver contain 16-byte FIFOs and data shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter. FEATURES -- -- -- -- RxD0,TxD0,RxD1,TxD1 with DMA-based or interrupt-based operation UART Ch 0 with IrDA 1.0 & 16-byte FIFO UART Ch 1 with IrDA 1.0 & 16-byte FIFO Supports handshake transmit / receive 10-1 UART S3C44B0X RISC MICROPROCESSOR BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO (16 Byte) Transmit Shifter TXDn Control Unit Buad-rate Generator Clock Source Receive Shifter RXDn Receive FIFO (16 Byte) Receiver Figure 10-1. UART Block Diagram (with FIFO) 10-2 S3C44B0X RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, loopback mode, infra-red mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (UCONn). The transmitter can also produce the break condition. The break condition forces the serial output to logic 0 state for a duration longer than one frame transmission time. This block transmit break signal after the present transmission word transmits perfectly. After the break signal transmit, continously transmit data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode). Data Reception Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (UCONn). The receiver can detect overrun error, parity error, frame error and break condition, each of which can set an error flag. - The overrun error indicates that new data has overwritten the old data before the old data has been read. - The parity error indicates that the receiver has detected an unexpected parity condition. - The frame error indicates that the received data does not have a valid stop bit. - The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time. Receive time-out condition occurs when it does not receive data during the 3 word time and the Rx FIFO is not empty in the FIFO mode. Auto Flow Control(AFC) S3C44B0X's UART supports auto flow control with nRTS and nCTS signals, in case it would have to connect UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS is controlled by condition of the receiver and operation of transmitter is controlled by the nCTS signal. The UART's transmitter transfers the data in FIFO only when nCTS signal active(In AFC, nCTS means that the other UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive FIFO has a spare more than 2-byte and has to be inactivated when its receive FIFO has a spare under 1-byte(In AFC, nRTS means that its own receive FIFO is ready to receive data). Transmission case in UART A UART A TxD nCTS UART B RxD nRTS Reception case in UART A UART A RxD nRTS UART B TxD nCTS Figure 10-2. UART AFC interface 10-3 UART S3C44B0X RISC MICROPROCESSOR Non Auto-Flow control(Controlling nRTS and nCTS by S/W) Rx operation 1. Select receive mode(Interrupt or BDMA mode) 2. Check the value of Rx FIFO count in UFSTATn register. If the value is less than 15, users have to set the value of UMCONn[0] to '1'(activate nRTS), and if it is equal or larger than 15 users have to set the value to '0'(inactivate nRTS). 3. Repeat item 2. Tx operation 1. Select transmit mode(Interrupt or BDMA mode) 2. Check the value of UMSTATn[0]. If the value is '1'(nCTS is activated), users write the data to Tx buffer or Tx FIFO register. RS-232C interface If users connect to modem interface(not equal null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are need. In this case, users control these signals with general I/O ports by S/W because the AFC does not support the RS-232C interface. 10-4 S3C44B0X RISC MICROPROCESSOR UART Interrupt/DMA Request Generation Each UART of S3C44B0X has seven status(Tx/Rx/Error) signals: Overrun error, Parity error, Frame error, Break, Receive FIFO/buffer data ready, Transmit FIFO/buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). The overrun error, parity error, frame error and break condition are referred to as the receive error status, each of which can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register UCONn. When a receive-error-status-interrupt-request is detected, the signal causing the request can be identified by reading UERSTSTn. When the receiver transfers the data of the receive shifter to the receive FIFO, it activates the receive FIFO full status signal which will cause the receive interrupt, if the receive mode in control register is selected as the interrupt mode. When the transmitter transfers data from its transmit FIFO to its transmit shifter, the transmit FIFO empty status signal is activated. The signal causes the transmit interrupt if the transmit mode in control register is selected as that interrupt mode. The receive-FIFO-full and transmit-FIFO-empty status signals can also be connected to generate the DMA request signals if the receive/transmit mode is selected as the DMA mode. Table 10-1. Interrupts In Connection with FIFO Type Rx interrupt FIFO Mode Each time receive data reaches the trigger level of receive FIFO, the Rx interrupt will be generated. When the FIFO is not empty and does not receive data during 3 word time, the Rx interrupt will be generated (receive time out). Tx interrupt Each time transmit data reaches the trigger level of transmit FIFO, the Tx interrupt will be generated. Frame error, parity error, and break signal are detected and received in bytes, and will generate an error interrupt. When it gets to the top of the receive FIFO, the error interrupt will be generated (overrun error). Each time transmit data become empty, the transmit holding register generates an interrupt. All errors generate an error interrupt immediately. However if another error occurs at the same time, only one interrupt is generated. Non-FIFO Mode Each time receive data becomes full, the receive shift register, generates an interrupt. Error interrupt 10-5 UART S3C44B0X RISC MICROPROCESSOR UART Error Status FIFO UART has the status FIFO besides the Rx FIFO register. The status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the status of FIFO, the URXHn with an error and UERSTATn must be read out. For example, It is assumed that the UART FIFO receives A, B, C, D, E characters sequentially and the frame error occurrs while receiving 'B' , and the parity error occurs while receiving 'D'. Although the UART error occurred, the error interrupt will not be generated because the character, which was received with an error, has not been read yet. The error interrupt will occur when the character is read out. Time #0 #1 #2 #3 #4 #5 Sequence Flow When no character is read out After A is read out After B is read out After C is read out After D is read out After E is read out Error Interrupt - The frame error(in B) interrupt occurs - The parity error(in D) interrupt occurs - - The 'D' has to be read out The 'B' has to be read out Note RX-FIFO break error 'E' 'D' 'C' 'B' 'A' URXHn STATUS-FIFO parity error frame error Error Status Generator Unit Figure 10-3. A Case showing UART Receiving 5 Characters with 2 Errors 10-6 S3C44B0X RISC MICROPROCESSOR UART Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for transmitter and receiver. The source clock for the baud-rate generator can be selected with the S3C44B0X's internal system clock. The baud-rate clock is generated by dividing the source clock by 16 and a 16-bit divisor specified in the UART baud-rate divisor register (UBRDIVn). The UBRDIVn can be determined as follows: UBRDIVn = (round_off)(MCLK/(bps x 16) ) -1 where the divisor should be from 1 to (216-1). For example, if the baud-rate is 115200 bps and MCLK is 40 MHz , UBRDIVn is: UBRDIVn = (int)(40000000/(115200 x 16)+0.5 ) -1 = (int)(21.7+0.5) -1 = 22 -1 = 21 Loop-back Mode The S3C44B0X UART provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link. In this mode, the transmitted data is immediately received. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel. This mode can be selected by setting the loopback-bit in the UART control register (UCONn). Break Condition The break is defined as a continuous low level signal for more than one frame transmission time on the transmit data output. 10-7 UART S3C44B0X RISC MICROPROCESSOR IR (Infrared) Mode The S3C44B0X UART block supports Infrared (IR) transmission and reception, which can be selected by setting the Infrared-mode bit in the UART control register (ULCONn). The implementation of the mode is shown in Figure 10-3. In IR transmit mode, the transmit period is pulsed at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); In IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (refer to the frame timing diagrams shown in Figures 10-5 and 10-6). Note: The received pulse is recognized by S3C44B0X which sampling frequency is 1/16 bit frame time, so when it communicates in low speed the Rx pulse must be longer than 1/16 bit frame time. In case of 9600baud rate, the Rx pulse width must be longer than 6.51us. (Bit frame width = 104.1us, sampling frequency = 6.51us) TxD 0 TxD 1 IRS UART Block RxD 1 RE 0 RxD IrDA Tx Encoder IrDA Rx Decoder Figure 10-4. IrDA Function Block Diagram 10-8 S3C44B0X RISC MICROPROCESSOR UART SIO Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 10-5. Serial I/O Frame Timing Diagram (Normal UART) IR Transmit Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Bit Time Pulse Width = 3/16 Bit Frame Figure 10-6. Infra-Red Transmit Mode Frame Timing Diagram IR Receive Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 10-7. Infra-Red Receive Mode Frame Timing Diagram 10-9 UART S3C44B0X RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are two UART line control registers, ULCON0 and ULCON1, in the UART block. Register ULCON0 ULCON1 Address 0x01D00000 0x01D04000 R/W R/W R/W Description UART channel 0 line control register UART channel 1 line control register Reset Value 0x00 0x00 ULCONn Reserved Infra-Red Mode Bit [7] [6] Description Initial State 0 The Infra-Red mode determines whether or not to use the InfraRed mode. 0 = Normal mode operation 1 = Infra-Red Tx/Rx mode The parity mode specifies how parity generation and checking are to be performed during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as 1 111 = Parity forced/checked as 0 The number of stop bits specifies how many stop bits are to be used to signal end-of-frame. 0 = One stop bit per frame 1 = Two stop bit per frame The word length indicates the number of data bits to be transmitted or received per frame. 00 = 5-bits 01 = 6-bits 10 = 7-bits 11 = 8-bits 0 Parity Mode [5:3] 000 Number of stop bit [2] 0 Word length [1:0] 00 10-10 S3C44B0X RISC MICROPROCESSOR UART UART CONTROL REGISTER There are two UART control registers, UCON0 and UCON1, in the UART block. Register UCON0 UCON1 Address 0x01D00004 0x01D04004 R/W R/W R/W Description UART channel 0 control register UART channel 1 control register Reset Value 0x00 0x00 UCONn Tx interrupt type Bit [9] Description Interrupt request type 0 = Pulse (Interrupt is requested the instant Tx buffer becomes empty) 1 = Level (Interrupt is requested while Tx buffer is empty) Interrupt request type 0 = Pulse (Interrupt is requested the instant Rx buffer receives the data) 1 = Level (Interrupt is requested while Rx buffer is receiving data) Enable/Disable Rx time out interrupt when UART FIFO is enabled. The interrupt is a receive interrupt. 0 = Disable 1 = Enable This bit enables the UART to generate an interrupt if an exception, such as a break, frame error, parity error, or overrun error occurs during a receive operation. 0 = Do not generate receive error status interrupt 1 = Generate receive error status interrupt Setting loop-back bit to 1 causes the UART to enter the loopback mode. This mode is provided for test purposes only. 0 = Normal operation 1 = Loop-back mode Setting this bit causes the UART to send a break during 1 frame time. This bit is auto-cleared after sending the break signal. 0 = Normal transmit 1 = Send break signal These two bits determine which function is currently able to write Tx data to the UART transmit holding register. 00 = Disable 01 = Interrupt request or polling mode 10 = BDMA0 request (Only for UART0) 11 = BDMA1 request (Only for UART1) These two bits determine which function is currently able to read data from UART receive buffer register. 00 = Disable, 01 = Interrupt request or polling mode 10 = BDMA0 request (Only for UART0) 11 = BDMA1 request (Only for UART1) Initial State 0 Rx interrupt type [8] 0 Rx time out enable [7] 0 Rx error status interrupt enable [6] 0 Loop-back Mode [5] 0 Send Break Signal [4] 0 Transmit Mode [3:2] 00 Receive Mode [1:0] 00 10-11 UART S3C44B0X RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are two UART FIFO control registers, UFCON0 and UFCON1, in the UART block. Register UFCON0 UFCON1 Address 0x01D00008 0x01D04008 R/W R/W R/W Description UART channel 0 FIFO control register UART channel 1 FIFO control register Reset Value 0x0 0x0 UFCONn Tx FIFO Trigger Level Rx FIFO Trigger Level Reserved Tx FIFO Reset Rx FIFO Reset FIFO Enable NOTE: Bit [7:6] Description These two bits determine the trigger level of transmit FIFO. 00 = Empty 01 = 4-byte 10 = 8-byte 11 = 12-byte These two bits determine the trigger level of receive FIFO. 00 = 4-byte 01 = 8-byte 10 = 12-byte 11 = 16-byte Initial State 00 [5:4] 00 [3] [2] [1] [0] This bit is auto-cleared after resetting FIFO 0 = Normal 1= Tx FIFO reset This bit is auto-cleared after resetting FIFO 0 = Normal 1= Rx FIFO reset 0 = FIFO disable 1 = FIFO mode 0 0 0 0 When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest. UART MODEM CONTROL REGISTER There are two UART MODEM control registers, UMCON0 and UMCON1, in the UART block. Register UMCON0 UMCON1 Address 0x01D0000C 0x01D0400C R/W R/W R/W Description UART channel 0 Modem control register UART channel 1 Modem control register Reset Value 0x0 0x0 UMCONn Reserved AFC(Auto Flow Control) Reserved Request to Send Bit [7:5] [4] [3:1] [0] These bits must be 0's 0 = Disable These bits must be 0's Description Initial State 00 1 = Enable 0 00 0 If AFC bit is enabled, this value will be ignored. In this case the S3C44B0X will control nRTS automatically. If AFC bit is disabled, nRTS must be controlled by S/W. 0 = 'H' level(Inactivate nRTS) 1 = 'L' level(Activate nRTS) 10-12 S3C44B0X RISC MICROPROCESSOR UART UART TX/RX STATUS REGISTER There are two UART Tx/Rx status registers, UTRSTAT0 and UTRSTAT1, in the UART block. Register UTRSTAT0 UTRSTAT1 Address 0x01D00010 0x01D04010 R/W R R Description UART channel 0 Tx/Rx status register UART channel 1 Tx/Rx status register Reset Value 0x6 0x6 UTRSTATn Transmit shifter empty Bit [2] Description This bit is automatically set to 1 when the transmit shift register has no valid data to transmit and the transmit shift register is empty. 0 = Not empty 1 = Transmit holding & shifter register empty This bit is automatically set to 1 when the transmit buffer register does not contain valid data. 0 =The buffer register is not empty 1 = Empty If the UART uses the FIFO, users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit. This bit is automatically set to 1 whenever the receive buffer register contains valid data, received over the RXDn port. 0 = Completely empty 1 = The buffer register has a received data If the UART uses the FIFO, users should check Rx FIFO Count bits in the UFSTAT register instead of this bit. Initial State 1 Transmit buffer empty [1] 1 Receive buffer data ready [0] 0 10-13 UART S3C44B0X RISC MICROPROCESSOR UART ERROR STATUS REGISTER There are two UART Rx error status registers, UERSTAT0 and UERSTAT1, in the UART block. Register UERSTAT0 UERSTAT1 Address 0x01D00014 0x01D04014 R/W R R Description UART channel 0 Rx error status register UART channel 1 Rx error status register Reset Value 0x0 0x0 UERSTATn Break Detect Bit [3] Description This bit is automatically set to 1 to indicate that a break signal has been received. 0 = No break receive 1 = Break receive This bit is automatically set to 1 whenever a frame error occurs during receive operation. 0 = No frame error during receive 1 = Frame error This bit is automatically set to 1 whenever a parity error occurs during receive operation. 0 = No parity error during receive 1 = Parity error This bit is automatically set to 1 whenever an overrun error occurs during receive operation. 0 = No overrun error during receive 1 = Overrun error Initial State 0 Frame Error [2] 0 Parity Error [1] 0 Overrun Error [0] 0 NOTE: These bits (UERSATn[3:0]) are automatically cleared to 0 when the UART error status register is read. 10-14 S3C44B0X RISC MICROPROCESSOR UART UART FIFO STATUS REGISTER Only the UARTn has a 16-byte transmit FIFO & a 16-byte receive FIFO. There are two UART FIFO status registers, UFSTAT0 and UFSTAT1, in the UART block. Register UFSTAT0 UFSTAT1 Address 0x01D00018 0x01D04018 R/W R R Description UART channel 0 FIFO status register UART channel 1 FIFO status register Reset Value 0x00 0x00 UFSTATn Reserved Tx FIFO Full Bit [15:10] [9] Description Initial State 0 This bit is automatically set to 1 whenever transmit FIFO is full during transmit operation 0 = 0-byte Tx FIFO data 15-byte 1 = Full This bit is automatically set to 1 whenever receive FIFO is full during receive operation 0 = 0-byte Rx FIFO data 15-byte 1 = Full Number of data in Tx FIFO Number of data in Rx FIFO 0 Rx FIFO Full [8] 0 Tx FIFO Count Rx FIFO Count [7:4] [3:0] 0 0 10-15 UART S3C44B0X RISC MICROPROCESSOR UART MODEM STATUS REGISTER There are two UART modem status register, UMSTAT0 and UMSTAT1, in the UART block. Register UMSTAT0 UMSTAT1 Address 0x01D0001C 0x01D0401C R/W R R Description UART channel 0 Modem status register UART channel 1 Modem status register Reset Value 0x0 0x0 UMSTATn Delta CTS Bit [4] Description This bit indicates that the nCTS input to S3C44B0X has changed state since the last time it was read by CPU. (Refer to Fig. 10-7) 0 = Has not changed 1 = Has changed Reserved 0 = CTS signal is not activated(nCTS pin is high) 1 = CTS signal is activated(nCTS pin is low) Initial State 0 Reserved Clear to Send [3:1] [0] 0 nCTS Delta CTS Read_UMSTATn Figure 10-8. nCTS and Delta CTS Timing diagram 10-16 S3C44B0X RISC MICROPROCESSOR UART UART TRANSMIT HOLDING(BUFFER) REGISTER & FIFO REGISTER UTXHn has an 8-bit data for transmission data Register UTXH0 UTXH1 Address 0x01D00020(L) 0x01D00023(B) 0x01D04020(L) 0x01D04023(B) R/W Description Reset Value - - W UART channel 0 transmit holding register (by byte) W UART channel 1 transmit holding register (by byte) UTXHn TXDATAn NOTE: Bit [7:0] Transmit data for UARTn Description Initial State - (L): When the endian mode is Little endian. (B): When the endian mode is Big endian. UART RECEIVE HOLDING (BUFFER) REGISTER & FIFO REGISTER URXHn has an 8-bit data for received data.. Register URXH0 Address 0x01D00024(L) 0x01D00027(B) URXH1 0x01D04024(L) 0x01D04027(B) R/W Description Reset Value - R UART channel 0 receive buffer register (by byte) R UART channel 1 receive buffer register (by byte) - URXHn RXDATAn NOTE: Bit [7:0] Receive data for UARTn Description Initial State - When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun error, even though the overrun bit of USTATn had been cleared. 10-17 UART S3C44B0X RISC MICROPROCESSOR UART BAUD RATE DIVISION REGISTER The value stored in the baud rate divisor register, UBRDIV, is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn = (round_off)(MCLK / (bps x 16) ) -1 where the divisor should be from 1 to (216-1). For example, if the baud-rate is 115200 bps and MCLK is 40 MHz, UBRDIVn is: UBRDIVn = (int)(40000000 / (115200 x 16)+0.5 ) -1 = (int)(21.7+0.5) -1 = 22 -1 = 21 Register UBRDIV0 UBRDIV1 Address 0x01D00028 0x01D04028 R/W R/W R/W Description Baud rate divisior register 0 Baud rate divisior register 1 Reset Value - - UBRDIV n UBRDIV Bit [15:0] Baud rate division value UBRDIVn > 0 Description Initial State - 10-18 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER 11 OVERVIEW INTERRUPT CONTROLLER The interrupt controller in S3C44B0X receives the request from 30 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, UARTand SIO, etc. In these interrupt sources, the four external interrupts(EINT4/5/6/7) are 'OR'ed to the interrupt controller. The UART0 and 1 Error interrupt are 'OR'ed , as well. The role of the interrupt controller is to ask for the FIQ or IRQ interrupt request to the ARM7TDMI core after making the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins. Originally, ARM7TDMI core only permits the FIQ or IRQ interrupt, which is the arbitration process based on priority by software. For example, if you define all interrupt source as IRQ (Interrupt Mode Setting), and, if there are 10 interrupt requests at the same time, you can determine the interrupt service priority by reading the interrupt pending register, which indicates the type of interrupt request that will occur. This kind of interrupt process requires a long interrupt latency until to jump to the exact service routine. (The S3C44B0X may support this kind of interrupt processing.) To solve the above-mentioned problem, S3C44B0X supports a new interrupt processing called vectored interrupt mode, which is a general feature of the CISC type micro-controller, to reduce the interrupt latency. In other words, the hardware inside the S3C44B0X interrupt controller provides the interrupt service vector directly. When the multiple interrupt sources request interrupts, the hardware priority logic determines which interrupt should be serviced. At same time, this hardware logic applies the jump instruction of the vector table to 0x18(or 0x1c), which performs the jump to the corresponding service routine. Compared with the previous software method, it will reduce the interrupt latency, dramatically. 11-1 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER OPERATION F-bit and I-bit of PSR (program status register) If the F-bit of PSR (program status register in ARM7TDMI CPU) is set to 1, the CPU does not accept the FIQ (fast interrupt request)from the interrupt controller. If I-bit of PSR (program status register in ARM7TDMI CPU) is set to 1, the CPU does not accept the IRQ (interrupt request)from the interrupt controller. So, to enable the interrupt reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be cleared to 0. Interrupt Mode ARM7TDMI has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of interrupt to be used at interrupt request. Interrupt Pending Register Indicates whether or not an interrupt request is pending. When a pending bit is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. Interrupt Pending Register is a read-only register, so the service routine must clear the pending condition by writing a 1 to I_ISPC or F_ISPC. Interrupt Mask Register Indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the pending bit will be set. If the global mask bit is set to 1, the interrupt pending bit will be set but all interrupts will not be serviced. 11-2 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES Among 30 interrupt sources, 26 sources are provided for the interrupt controller. Four external interrupt (EINT4/5/6/7) requests are ORed to provide a single interrupt source to the interrupt controller, and two UART error interrupts (UERROR0/1) are the same configuration. Sources EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC NOTE: Descriptions External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4/5/6/7 RTC Time tick interrupt General DMA0 interrupt General DMA1 interrupt Bridge DMA0 interrupt Bridge DMA1 interrupt Watch-Dog timer interrupt UART0/1 error Interrupt Timer0 interrupt Timer1 interrupt Timer2 interrupt Timer3 interrupt Timer4 interrupt Timer5 interrupt UART0 receive interrupt UART1 receive interrupt IIC interrupt SIO interrupt UART0 transmit interrupt UART1 transmit interrupt RTC alarm interrupt ADC EOC interrupt Master Group mGA mGA mGA mGA mGA mGA mGB mGB mGB mGB mGB mGB mGC mGC mGC mGC mGC mGC mGD mGD mGD mGD mGD mGD mGKA mGKB Slave ID sGA sGB sGC sGD sGKA sGKB sGA sGB sGC sGD sGKA sGKB sGA sGB sGC sGD sGKA sGKB sGA sGB sGC sGD sGKA sGKB - - EINT4, EINT5, EINT6, and EINT7 share the same interrupt request line. Therefore, the ISR (interrupt service routine) will discriminate these four interrupt sources by reading the EXTINPND[3:0] register. EXTINPND[3:0] must be cleared by writing a 1 in the ISR after the corresponding ISR has been completed. 11-3 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR INTERRUPT PRIORITY GENERATING BLOCK There is the interrupt priority generating block only for IRQ interrupt request. If the vectored mode is used and an interrupt source is configured as ISR in INTMOD register, the interrupt will be processed by the interrupt priority generating block. The priority generating block consists of five units, 1 master unit and 4 slave units. Each slave priority generating unit manages six interrupt sources. The master priority generating unit manages 4 slave units and 2 interrupt sources. Each slave unit has 4 programmable priority sources (sGn) and 2 fixed priotiry sources (sGKn). The priority among the 4 sources in each slave unit is programmable. The other 2 fixed priorities have the lowest priority among the 6 sources. The master priority generating unit determines the priority between the 4 slave units and 2 interrupt sources. The 2 interrupt sources, INT_RTC and INT_ADC, have the lowest priority among 26 interrupt sources. mGA mGA, B, C, D ARM IRQ mGKA, B mGB sGA, B, C, D sGKA, B EINT0, 1, 2, 3 EINT4/5/6/7 TICK sGA, B, C, D sGKA, B ZDMA0, ZD MA1 BRDMA0, BRDMA1 WDT UERR0/1 mGC sGA, B, C, D sGKA, B TIMER0, 1, 2, 3 TIMER4, 5 mGD sGA, B, C, D sGKA, B RXD0, 1 IIC, SIO TXD0, 1 RTC ADC mGKA mGKB Figure 11-1. Priority Generating Block 11-4 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY If source A is configured to FIQ and source B is configured to IRQ, source A has higher priority than source B because a FIQ interrupt has higher priority than an IRQ interrupt in all cases. If source A and source B are in different master groups and the master group priority of source A is higher than the master group priority of source B, the priority of source A is higher than source B. If source A and source B are in the same master group and source A has higher priority than source B, source A has the higher priority. The priorities of sGA, sGB, sGC, and sGD are always higher than those of sGKA and sGKB. The priorities among sGA,sGB,sGC and sGD are programmable or are determined by the round-robin method. Between sGKA and sGKB, sGKA has always the higher priority. The group priority of mGA, mGB, mGC, and mGD are always higher than that of mGKA and mGKB. So, the priorities of mGKA and mGKB are the lowest among the other interrupt sources. The group priority among mGA, mGB, mGC and, mGD is programmable or is determined by the round-robin method. Between mGKA and mGKB, mGKA always has the higher priority. VECTORED INTERRUPT MODE (ONLY FOR IRQ) S3C44B0X has a new feature, the vectored interrupt mode, to reduce the interrupt latency time. If ARM7TDMI receives the IRQ interrupt request from the interrupt controller, ARM7TDMI executes an instruction at 0x00000018. In vectored interrupt mode, the interrupt controller will load branch instructions on the data bus when ARM7TDMI fetches the instructions at 0x00000018. The branch instructions let the program counter be a unique address corresponding to each interrupt source. The interrupt controller generates the machine code for branching to the vector address of each interrupt source. For example, If EINT0 is IRQ, the interrupt controller must generate the branch instruction which branches from 0x18 to 0x20. So, the interrupt controller generates the machine code, 0xea000000. The user program code must locate the branch instruction, which branches to the corresponding ISR (interrupt service routine) at each vector address. The machine code, branch instruction, at the corresponding vector address is calculated as follows; Branch Instruction machine code for vectored interrupt mode = 0xea000000 +(( 11-5 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR Interrupt Sources EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC Vector Address 0x00000020 0x00000024 0x00000028 0x0000002c 0x00000030 0x00000034 0x00000040 0x00000044 0x00000048 0x0000004c 0x00000050 0x00000054 0x00000060 0x00000064 0x00000068 0x0000006c 0x00000070 0x00000074 0x00000080 0x00000084 0x00000088 0x0000008c 0x00000090 0x00000094 0x000000a0 0x000000c0 11-6 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER EXAMPLE OF VECTORED INTERRUPT MODE In the vectored interrupt mode, CPU will branch to each interrupt address when an interrupt request is generated. So, there must be the branch instruction to jump each corresponding ISR on it's own address as follows; ENTRY b ResetHandler b HandlerUndef b HandlerSWI b HandlerPabort b HandlerDabort b. b HandlerIRQ b HandlerFIQ ldr pc,=HandlerEINT0 ldr pc,=HandlerEINT1 ldr pc,=HandlerEINT2 ldr pc,=HandlerEINT3 ldr pc,=HandlerEINT4567 ldr pc,=HandlerTICK b. b. ldr pc,=HandlerZDMA0 ldr pc,=HandlerZDMA1 ldr pc,=HandlerBDMA0 ldr pc,=HandlerBDMA1 ldr pc,=HandlerWDT ldr pc,=HandlerUERR01 b. b. ldr pc,=HandlerTIMER0 ldr pc,=HandlerTIMER1 ldr pc,=HandlerTIMER2 ldr pc,=HandlerTIMER3 ldr pc,=HandlerTIMER4 ldr pc,=HandlerTIMER5 b. b. ldr pc,=HandlerURXD0 ldr pc,=HandlerURXD1 ldr pc,=HandlerIIC ldr pc,=HandlerSIO ldr pc,=HandlerUTXD0 ldr pc,=HandlerUTXD1 b. b. ldr pc,=HandlerRTC b. b. b. b. b. b. ldr pc,=HandlerADC ; ; ; ; ; ; ; ; 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c ; 0x20 ; 0x34 ; 0x40 ; 0x54 ; 0x60 ; 0x74 ; 0x80 ; 0x94 ; 0xa0 ; 0xb4 11-7 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR EXAMPLE FOR NON-VECTORED INTERRUPT MODE USING I_ISPR In the non-vectored interrupt mode, the IRQ/FIQ handler will move the PC to the corresponding ISR by analyzing I_ISPR/F_ISPR register. HandleXXX addresses hold each corresponding ISR routine start addresses. The source code for an IRQ interrupt is as follows; ENTRY b ResetHandler b HandlerUndef b HandlerSWI b HandlerPabort b HandlerDabort b. b IsrIRQ b HandlerFIQ ...... IsrIRQ sub stmfd ldr ldr mov movs bcs add b sp,sp,#4 sp!,{r8-r9} r9,=I_ISPR r9,[r9] r8,#0x0 r9,r9,lsr #1 %F1 r8,r8,#4 %B0 r9,=HandleADC r9,r9,r8 r9,[r9] r9,[sp,#8] sp!,{r8-r9,pc} 4 4 4 4 4 4 4 4 ; ; ; ; ; ; for debug handlerUndef SWI interrupt handler handlerPAbort handlerDAbort handlerReserved ; reserved for PC 0 1 ldr add ldr str ldmfd ...... HandleADC # HandleRTC # HandleUTXD1 # HandleUTXD0 # ...... HandleEINT3 # HandleEINT2 # HandleEINT1 # HandleEINT0 # ; 0xc1(c7)fff84 11-8 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS INTERRUPT CONTROL REGISTER (INTCON) Register INTCON Address 0x01E00000 R/W R/W Description Interrupt control Register Reset Value 0x7 INTCON Reserved V Bit [3] [2] 0 Description initial state 0 1 This bit disables/enables vector mode for IRQ 0 = Vectored interrupt mode 1 = Non-vectored interrupt mode This bit enables IRQ interrupt request line to CPU 0 = IRQ interrupt enable 1 = Reserved Note : Before using the IRQ interrupt this bit must be cleared. This bit enables FIQ interrupt request line to CPU 0 = FIQ interrupt enable (Not allowed vectored interrupt mode) 1 = Reserved Note : Before using the FIQ interrupt this bit must be cleared. I [1] 1 F [0] 1 NOTE: FIQ interrupt mode does not support vectored interrupt mode. 11-9 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR INTERRUPT PENDING REGISTER (INTPND) Each of the 26 bits in the interrupt pending register, INTPND, corresponds to an interrupt source. When an interrupt request is generated, it will be set to 1. The interrupt service routine must then clear the pending condition by writing '1' to the corresponding bit of I_ISPC/F_ISPC. Although several interrupt sources generate requests simultaneously, the INTPND will indicate all interrupt sources that generate an interrupt request. Even if the interrupt source is masked by INTMSK, the corresponding pending bit can be set to 1. Register INTPND Address 0x01E00004 R/W R Description Indicates the interrupt request status. 0 = The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request Reset Value 0x0000000 INTPND EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC Bit [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11-10 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER INT_ADC [0] 0 = Not requested, 1 = Requested 0 11-11 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR INTERRUPT MODE REGISTER (INTMOD) Each of the 26 bits in the interrupt mode register, INTMOD, corresponds to an interrupt source. When the interrupt mode bit for each source is set to 1, the interrupt is processed by the ARM7TDMI core in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). The 26 interrupt sources are summarized as follows: Register INTMOD Address 0x01E00008 R/W R/W Description Interrupt mode Register 0 = IRQ mode 1 = FIQ mode Reset Value 0x0000000 INTMOD EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC Bit [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode 0 = IRQ mode Description 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode 1 = FIQ mode initial state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11-12 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MASK REGISTER (INTMSK) Each of the 26 bits except the global mask bit in the interrupt mask register, INTMSK, corresponds to an interrupt source. When a source interrupt mask bit is 1 and the corresponding interrupt event occurs, the interrupt is not serviced by the CPU. If the mask bit is 0, the interrupt is serviced upon a request. If the global mask bit is set to 1, all interrupt requests are not serviced, and the INTPND register is set to 1. If the INTMSK is changed in ISR(interrupt service routine) and the vectored interrupt is used, an INTMSK bit can not mask an interrupt event, which had been latched in INTPND before the INTMSK bit was set. To clear this problem, clear the corresponding pending bit(INTPND) after changing INTMSK. The 26 interrupt sources and global mask bit are summarized as follows: Register INTMSK Address 0x01E0000C R/W R/W Description Determines which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available 1 = Interrupt service is masked IMPORTANT NOTES 1. INTMSK register can be masked only when it is sure that the corresponding interrupt does not be requested. If your application should mask any interrupt mask bit(INTMSK) just when the corresponding interrupt is issued, please contact our FAE (field application engineer). 2. If you need that all interrupt is masked, we recommend that I/F bits in CPSR are set using MRS, MSR instructions. The I, F bit in CPSR can be masked even when any interrupt is issued. Reset Value 0x07ffffff 11-13 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTMSK Reserved Global EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC Bit [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available 0 = Service available Description initial state 0 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11-14 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER IRQ VECTORED MODE REGISTERS The priority generating block consists of five units, 1 master unit and 4 slave units. Each slave priority generating unit manages six interrupt sources. The master priority generating unit manages 4 slave units and 2 interrupt sources. Each slave unit has 4 programmable priority source (sGn) and 2 fixed priority sources (kn). The priority among the 4 sources in each slave unit is determined the I_PSLV register. The other 2 fixed priorities have the lowest priority among the 6 sources. The master priority generating unit determines the priority between 4 slave units and 2 interrupt sources using the I_PMST register. The 2 interrupt sources,INT_RTC and INT_ADC, have the lowest priority among the 26 interrupt sources. If several interrupts are requested at the same time, the I_ISPR register shows only the requested interrupt source with the highest priority. Register I_PSLV I_PMST I_CSLV I_CMST I_ISPR I_ISPC Address 0x01E00010 0x01E00014 0x01E00018 0x01E0001C 0x01E00020 0x01E00024 R/W R/W R/W R R R W Description IRQ priority of slave register IRQ priority of master register Current IRQ priority of slave register Current IRQ priority of master register IRQ interrupt service pending register (Only one service bit can be set) IRQ interrupt service clear register (Whatever to be set, INTPND will be cleared automatically) IMPORTANT NOTE In FIQ mode, there is no service pending register like I_ISPR, users must check INTPND resister. Reset Value 0x1b1b1b1b 0x00001f1b 0x1b1b1b1b 0x0000xx1b 0x00000000 Undef. 11-15 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR IRQ PRIORITY OF SLAVE REGISTER (I_PSLV) I_PSLV determines the interrupt priorities among the 4 interrupt sources of each slave group. Register I_PSLV Address 0x01E00010 R/W R/W Description IRQ priority of slave register Reset Value 0x1b1b1b1b I_PSLV PSLAVE@mGA PSLAVE@mGB PSLAVE@mGC PSLAVE@mGD Bit [31:24] [23:16] [15:8] [7:0] Description Determine the priorities among sGA, B, C, D of mGA. Each sGn must have a different priority. Determine the priorities among sGA, B, C, D of mGB. Each sGn must have a different priority. Determine the priorities among sGA, B, C, D of mGC. Each sGn must have a different priority. Determine the priorities among sGA, B, C, D of mGD. Each sGn must have a different priority. Initial State 0x1b 0x1b 0x1b 0x1b PSLAVE@mGA sGA (EINT0) sGB (EINT1) sGC (EINT2) sGD (EINT3) Bit [31:30] [29:28] [27:26] [25:24] 00: 1st 00: 1 00: 1 st st Description 01: 2nd 01: 2 01: 2 nd nd Initial State 00 01 10 11 10: 3rd 10: 3 10: 3 rd rd 11: 4th 11: 4 11: 4 th th 00: 1st 01: 2nd 10: 3rd 11: 4th PSLAVE@mGB sGA (INT_ZDMA0) sGB (INT_ZDMA1) sGC (INT_BDMA0) sGD (INT_BDMA1) Bit [23:22] [21:20] [19:18] [17:16] 00: 1 00: 1 00: 1 00: 1 st st st st Description 01: 2 01: 2 01: 2 01: 2 nd nd nd nd Initial State 00 01 10 11 10: 3 10: 3 10: 3 10: 3 rd rd rd rd 11: 4 11: 4 11: 4 11: 4 th th th th 11-16 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER PSLAVE@mGC sGA (TIMER0) sGB (TIMER1) sGC (TIMER2) sGD (TIMER3) Bit [15:14] [13:12] [11:10] [9:8] 00: 1 st Description 01: 2 nd Initial State 00 01 10 11 10: 3 rd 11: 4 th 00: 1st 00: 1 00: 1 st st 01: 2nd 01: 2 01: 2 nd nd 10: 3rd 10: 3 10: 3 rd rd 11: 4th 11: 4 11: 4 th th PSLAVE@mGD sGA (INT_URXD0) sGB (INT_URXD1) Sgc (INT_IIC) sGD (INT_SIO) NOTE: Bit [7:6] [5:4] [3:2] [1:0] 00: 1st 00: 1 00: 1 00: 1 st st st Description 01: 2nd 01: 2 01: 2 01: 2 nd nd nd Initial State 00 01 10 11 10: 3rd 10: 3 10: 3 10: 3 rd rd rd 11: 4th 11: 4 11: 4 11: 4 th th th The items in I_PSLAVE must be configured with different priorities even if the corresponding interrupt source is not used. 11-17 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR IRQ PRIORITY OF MASTER REGISTER (I_PMST) I_PMST determines the interrupt priorities among the 4 slave groups. Register I_PMST Address 0x01E00014 R/W R/W Description IRQ priority of master register Reset Value 0x00001f1b I_PMST Reserved M FxSLV[A:D] PMASTER Bit [15:13] [12] [11:8] [7:0] Description Initial State 000 Master operating mode 0 = round robin 1 = fix mode Slave operating mode 0 = round robin 1 = fix mode 1 1111 0x1b Determine the priorities among 4 slave units. FxSLV Fx@mGA Fx@mGB Fx@mGC Fx@mGD Bit [11] [10] [9] [8] Description Determines the operating mode of slave unit @mGA Determines the operating mode of slave unit @mGB Determines the operating mode of slave unit @mGC Determines the operating mode of slave unit @mGD Initial State 1 1 1 1 PMASTER mGA mGB mGC mGD NOTE: Bit [7:6] [5:4] [3:2] [1:0] 00: 1 00: 1 00: 1 00: 1 st st st st Description 01: 2 01: 2 01: 2 01: 2 nd nd nd nd Initial State 00 01 10 11 10: 3 10: 3 10: 3 10: 3 rd rd rd rd 11: 4 11: 4 11: 4 11: 4 th th th th The items in I_PMST must be configured with different priorities even if the corresponding interrupt source is not used. 11-18 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER CURRENT IRQ PRIORITY OF SLAVE REGISTER (I_CSLV) I_CSLV indicates the current priority status among the sources in each slave group. The I_CSLV may differ from I_PSLV if the round-robin mode is enabled. Register I_CSLV Address 0x01E00018 R/W R Description Current IRQ priorities of slave register Reset Value 0x1b1b1b1b I_CSLV CSLAVE@mGA CSLAVE@mGB CSLAVE@mGC CSLAVE@mGD Bit [31:24] [23:16] [15:8] [7:0] Description Indicate the current priority status of mGA Indicate the current priority status of mGB Indicate the current priority status of mGC Indicate the current priority status of mGD Initial State 0x1b 0x1b 0x1b 0x1b CSLAVE@mGA sGA (EINT0) sGB (EINT1) sGC (EINT2) sGD (EINT3) Bit [31:30] [29:28] [27:26] [25:24] 00: 1st 00: 1st 00: 1st 00: 1st 01: 2nd 01: 2nd 01: 2nd 01: 2nd Description 10: 3rd 11: 4th 10: 3rd 11: 4th 10: 3rd 11: 4th 10: 3rd 11: 4th Initial State 00 01 10 11 CSLAVE@mGB sGA (INT_ZDMA0) sGB (INT_ZDMA1) sGC (INT_BDMA0) sGD (INT_BDMA1) Bit [23:22] [21:20] [19:18] [17:16] 00: 1 00: 1 00: 1 00: 1 st st st st Description 01: 2 01: 2 01: 2 01: 2 nd nd nd nd Initial State th th th th 10: 3 rd rd rd rd 11: 4 00 01 10 11 10: 3 10: 3 10: 3 11: 4 11: 4 11: 4 CSLAVE@mGC sGA (TIMER0) sGB (TIMER1) sGC (TIMER2) sGD (TIMER3) Bit [15:14] [13:12] [11:10] [9:8] 00: 1 00: 1 st st Description 01: 2 01: 2 nd nd Initial State th th 10: 3 rd rd 11: 4 00 01 10 11 10: 3 11: 4 00: 1st 00: 1 st 01: 2nd 01: 2 nd 10: 3rd 10: 3 rd 11: 4th 11: 4 th CSLAVE@mGD sGA (INT_URXD0) sGB (INT_URXD1) sGC (INT_IIC) sGD (INT_SIO) Bit [7:6] [5:4] [3:2] [1:0] 00: 1 st Description 01: 2 nd Initial State th 10: 3 rd 11: 4 00 01 10 11 00: 1st 00: 1 00: 1 st st 01: 2nd 01: 2 01: 2 nd nd 10: 3rd 10: 3 10: 3 rd rd 11: 4th 11: 4 11: 4 th th 11-19 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR CURRENT IRQ PRIORITY OF MASTER REGISTER (I_CMST) I_CMST indicates the current priority status among the slave groups Register I_CMST Address 0x01E0001C R/W R Description Current IRQ priority of master register Reset Value 0x0000xx1b I_CMST Reserved VECTOR CMASTER Bit [15:14] [13:8] [7:0] Description Initial State 00 The lower 6 bits of corresponding branch machine code Current priority of master unknown 00011011 CMASTER mGA mGB mGC mGD Bit [7:6] [5:4] [3:2] [1:0] 00: 1 st Description 01: 2nd 01: 2nd 01: 2nd 01: 2nd 10: 3rd 11: 4th 10: 3rd 11: 4th 10: 3rd 11: 4th 10: 3rd 11: 4th 00: 1st 00: 1 00: 1 st st Initial State 00 01 10 11 11-20 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER IRQ INTERRUPT SERVICE PENDING REGISTER (I_ISPR) I_ISPR indicates the interrupt being currently serviced. Although the several interrupt pending bits are all turned on, only one bit will be turned on. Register I_ISPR Address 0x01E00020 R/W R Description IRQ interrupt service pending register Reset Value 0x00000000 I_ISPR EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC Bit [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced 0 = not serviced Description 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now 1 = serviced now Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11-21 INTERRUPT CONTROLLER S3C44B0X RISC MICROPROCESSOR IRQ/FIQ INTERRUPT SERVICE PENDING CLEAR REGISTER (I_ISPC/F_ISPC) I_ISPC/F_ISPC clears the interrupt pending bit (INTPND). I_ISPC/F_ISPC also informs the interrupt controller of the end of corresponding ISR (interrupt service routine). At the end of ISR(interrupt service routine), the corresponding pending bit must be cleared. The bit of INTPND bit is cleared to zero by writing '1' on I_ISPC/F_ISPC. This feature reduces the code size to clear the INTPND. The corresponding INTPND bit is cleared automatically by I_ISPC/F_ISPC, INTPND register can not be cleared directly. NOTE To clear the I_ISPC/F_ISPC, the following two rules has to be obeyed. 1) The I_ISPC/F_ISPC registers are accessed only once in ISR(interrupt service routine). 2) The pending bit in I_ISPR/INTPND register should be cleared by writing I_ISPC register. If these two rules are not followed, I_ISPR and INTPND register may be 0 although the interrupt has been requested. Register I_ISPC F_ISPC Address 0x01E00024 0x01E0003C R/W W W Description IRQ interrupt service pending clear register FIQ interrupt service pending clear register Reset Value Undef. Undef. 11-22 S3C44B0X RISC MICROPROCESSOR INTERRUPT CONTROLLER I_ISPC/F_ISPC EINT0 EINT1 EINT2 EINT3 EINT4/5/6/7 INT_TICK INT_ZDMA0 INT_ZDMA1 INT_BDMA0 INT_BDMA1 INT_WDT INT_UERR0/1 INT_TIMER0 INT_TIMER1 INT_TIMER2 INT_TIMER3 INT_TIMER4 INT_TIMER5 INT_URXD0 INT_URXD1 INT_IIC INT_SIO INT_UTXD0 INT_UTXD1 INT_RTC INT_ADC Bit [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change 0 = No change Description 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit 1 = clear the pending bit Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11-23 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER 12 OVERVIEW LCD CONTROLLER The LCD controller within S3C44B0X consists of logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering algorithm and FRC (Frame Rate Control) method. It can support 8-bit per pixel (256 level color) for interfacing with a color LCD panel, also. The LCD controller can be programmed to support the different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. FEATURES -- -- -- -- -- -- Supports color/gray/monochrome LCD panels. Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type. Supports Multiple Virtual Display Screen. (Supports Hardware Horizontal/Vertical Scrolling) The system memory is used as the display memory. Dedicated DMA supports to fetch the image data from video buffer located in system memory. Supports multiple screen size. Typical actual screen sizes: 640x480, 320x240, 160x160 (pixels) Maximum virtual screen sizes(color mode): 4096x1024, 2048x2048, 1024x4096, etc Supports the monochrome, 4 gray levels, and 16 gray levels . Supports 256 level colors for color STN LCD panel. Supports the power saving mode(SL_IDLE Mode). -- -- -- 12-1 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR EXTERNAL INTERFACE SIGNAL VFRAME: This is the frame synchronous signal between the LCD controller and LCD driver. It signals the LCD panel of the start of a new frame. The LCD controller asserts VFRAME after a full frame of display as shown in Fig. 12-3. This is the line synchronous pulse signal between LCD controller and LCD driver, and it is used by the LCD driver to transfer the contents of it's horizontal line shift register to the LCD panel for display. The LCD controller asserts VLINE after an entire horizontal line of data has been shifted into the LCD driver. This pin is the pixel clock signal between the LCD controller and LCD driver, and data is sent by the LCD controller on the rising edge of VCLK and sampled by LCD driver on the falling edge of VCLK. This is the AC signal for the LCD driver. The VM signal is used by the LCD driver to alternate the polarity of the row and column voltage used to turn the pixel on and off. The VM signal can be toggled on every frame or toggled on the programmable number of the VLINE signal. These are LCD pixel data output ports. For a 4-bit or 8-bit single scan display, these 4-bit data are used as the display data as shown in Fig. 12-4. In case of 4-bit dual scan display, these plays into its role of the upper display data as shown in Fig. 12-4. VD[7:4]: These are LCD pixel data output ports. For a 8-bit single scan display, these data are used as upper dispaly data as shown in Fig. 12-4. For a 4-bit dual scan display, these data are used as lower display data as shown in Fig. 12-4. VLINE: VCLK: VM: VD[3:0]: 4-bit 12-2 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER BLOCK DIAGRAM System Bus REGBANK TIMEGEN VCLK VLINE VFRAME VM 32 LCDCDMA 32 32 VD[3:0] VIDPRCS VD[7:4] Figure 12-1. LCD Controller Block Diagram The LCD controller within S3C44B0X is used to transfer the video data and to generate the necessary control signals such as, VFRAME, VLINE, VCLK, and VM. As well as the control signals, S3C44B0X has the data ports of video data, which are VD[7:0] as shown in Fig. 12-1. The LCD controller consists of a REGBANK, LCDCDMA, VIDPRCS, and TIMEGEN (See Figure 12-1 LCD Controller Block Diagram). The REGBANK has 18 programmable register sets which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which it can transfer the video data in frame memory to LCD driver, automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from LCDCDMA and sends the video data through the VD[7:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. The TIMEGEN consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on. The description of data flow is as follows: FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode(Consecutive memory fetching of 4 words(16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When this kind of transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 24 words, which consists of FIFOL and FIFOH of 12 words. The S3C44B0X has two FIFOs because it needs to support the dual scan display mode. In case of single scan mode, one of them can only be used. 12-3 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER OPERATION TIMING GENERATOR The TIMEGEN generates the control signals for LCD driver such as, VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2 register in the REGBANK. Based on these programmable configurations on the LCD control registers in REGBANK, the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers. The VFRAME pulse is asserted for a duration of the entire first line at a frequency of once per frame. The VFRAME signal is asserted to bring the LCD's line pointer to the top of the display to start over. The VM signal is used by the LCD driver to alternate the polarity of the row and column voltage used to turn the pixel on and off. The toggle rate of VM signal can be controlled by using the MMODE bit of LCDCON 1 register and MVAL[7:0] field of LCDSADDR 2 register. If the MMODE bit is 0, the VM signal is configured to toggle on every frame. If the MMODE bit is 1, the VM signal is configured to toggle on the every number of VLINE signal by the MVAL[7:0] value. Figure 12-3 shows an example for MMODE=0 and for MMODE=1 with the value of MVAL[7:0]=0x2. When MMODE=1, the VM rate is related to MVAL[7:0], as shown below: VM Rate = VLINE Rate / ( 2 * MVAL) The VFRAME and VLINE pulse generation is controlled by the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2 register. Each field is related to the LCD size and display mode. In other words, the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation: HOZVAL = ( Horizontal display size / Number of the valid VD data line) -1 In color mode: Horizontal display size = 3 * Number of Horizontal Pixel In case of 4-bit dual scan display the number of valid VD data line should be 4 and in case of 8-bit signal scan display mode, the number of valid VD data lines should be 8. LINEVAL = (Vertical display size) -1: In case of single scan display type LINEVAL = (Vertical display size / 2) -1: In case of dual scan display type The rate of VCLK signal can be controlled by the CLKVAL field in the LCDCON1 register. The Table 12-1 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 2. VCLK(Hz)=MCLK/(CLKVAL x 2) The frame rate is the VFRAM signal frequency. The frame rate is closely related to the field of WLH(VLINE pulse width), WHLY(the delay width of VCLK after VLINE pulse), HOZVAL, VLINEBLANK, and LINEVAL in LCDCON1 and LCDCON2 registers as well as VCLK and MCLK. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows; frame_rate(Hz) = 1 / [ ( (1/VCLK) x (HOZVAL+1)+(1/MCLK) x (WLH+WDLY+LINEBLANK) ) x ( LINEVAL+1) ] VCLK(Hz) = (HOZVAL+1) / [ (1 / (frame_rate x (LINEVAL+1))) - ((WLH+WDLY+LINEBLANK) / MCLK )] 12-4 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER Table 12-1. Relation between VCLK and CLKVAL(MCLK=60MHz) CLKVAL 2 3 : 1023 60MHz/X 60 MHz/4 60 MHz/6 : 60 MHz/2046 VCLK 15.0 MHz 10.0 MHz : 29.3 kHz VIDEO OPERATION The LCD controller within S3C44B0X supports 8-bit color mode(256 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode. When the gray or color mode is needed, the time-based dithering algorithm and FRC(Frame Rate Control) method can be used to implement the shades of gray or color from which selection can be made by using a programmable lockup table, which will be explained later. The monochrome mode bypasses these modules(FRC and lookup table) and basically serializes the data in FIFOH (and FIFOL if a dual scan display type is used) into 4-bit (or 8-bit if a 4-bit dual scan or 8-bit single scan display type is used) streams by shifting the video data to the LCD driver. The following sections describe the operation on gray mode and color mode in terms of the lookup table and FRC. Lookup Table The S3C44B0X can support the palette table for various selection of color or gray level mapping. This kind of selection gives users flexibility. The lookup table is the palette which allows the selection on the level of color or gray(Selection on 4-gray levels among 16 gray levels in case of gray mode, selection on 8 red levels among 16 levels, 8 green levels among 16 levels and 4 blue levels among 16 levels in case of color mode). In other words, users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode.The gray levels cannot be selected in the 16 gray level mode; all 16 gray levels must be chosen among the possible 16 gray levels. In case of 256 color mode, 3 bits are allocated for red, 3 bits for green and 2 bits for blue. The 256 colors mean that the colors are formed from the combination of 8 red, 8 green and 4 blue levels(8x8x4 = 256). In the color mode, the lookup table can be used for suitable selections. Eight red levels can be selected among 16 possible red levels, 8 green levels among 16 green levels, and 4 blue levels among 16 blue levels. Gray Mode Operation Two gray modes are supported by the LCD controller within the S3C44B0X: 2-bit per pixel gray (4 level gray scale) or 4-bit per pixel gray (16 level gray scale). The 2-bit per pixel gray mode uses a lookup table, which allows selection on 4 gray levels among 16 possible gray levels. The 2-bit per pixel gray lookup table uses the BULEVAL[15:0] in BLUELUT(Blue Lookup Table) register as same as blue lookup table in color mode. The gray level 0 will be denoted by BLUEVAL[3:0] value. If BLUEVAL[3:0] is 9, level 0 will be represented by gray level 9 among 16 gray levels. If BLUEVAL[3:0] is 15, level 0 will be represented by gray level 15 among 16 gray levels, and so on. As same as in the case of level 0, level 1 will also be denoted by BLUEVAL[7:4], the level 2 by BLUEVAL[11:8], and the level 3 by BLUEVAL[15:12]. These four groups among BLUEVAL[15:0] will represent level 0, level 1, level 2, and level 3. In 16 gray levels, of course there is no selection as in the 4 gray levels. 12-5 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR Color Mode Operation The LCD controller in S3C44B0X can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. The color display mode uses separate lookup tables for red, green, and blue. Each lookup table uses the REDVAL[31:0] of REDLUT register, GREENVAL[31:0] of GREENLUT register, and BLUEVAL[15:0] of BLUELUT register as the programmable lookup table entries. Similarly with the gray level display, 8 group or field of 4 bits in the REDLUR register, i.e., REDVAL[31:28], REDLUT[27:24], REDLUT[23:20], REDLUT[19:16], REDLUT[15:12], REDLUT[11:8], REDLUT[7:4], and REDLUT[3:0], are assigned to each red level. The possible combination of 4 bits(each field) is 16, and each red level should be assigned to one level among possible 16 cases. In other words, the user can select the suitable red level by using this type of lookup table. For green color, the GREENVAL[31:0] of the GREENLUT register is assigned as the lookup table, as was done in the case of red color. Similarly, the BLUEVAL[15:0] of the BLUELUT register is also assigned as a lookup table. For blue color, we need 16bit for a lookup table because 2 bits are allocated for 4 blue levels, different from the 8 red or green levels. 12-6 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER DITHERING AND FRC (FRAME RATE CONTROL) The DITHFRC block has two functions, such as a Time-based Dithering Algorithm for reducing flicker and FRC(Frame Rate Control) for displaying gray level on the STN panel. The main principle of gray level display on the STN panel based on FRC is described. For example, to display the third gray(3/16) level from a total of 16 levels, the 3 times pixel should be on and 13 times pixel off. In other words, 3 frames should be selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining 13 frames should have a pixel-off on a specific pixel. These 16 frames should be displayed periodically. This is basic principle on how to display the gray level on the screen, so-called gray level display by FRC(Frame Rate Control). The actual example is shown in Table 12-2. To represent the 14th gray level in the table, we should have a 6/7 duty cycle, which mean that there are 6 times pixel-on and one time pixel-off. The other cases for all gray levels are also shown in Table 12-2. In the STN LCD display, we should be reminded of one item, i.e., Flicker Noise due to the simultaneous pixel-on and -off on adjacent frames. For example, if all pixels on first frame are turned on and all pixels on next frame are turned off, the Flicker Noise will be maximized. To reduce the Flicker Noise on the screen, the average probability of pixelon and -off between frames should be as same as possible. In order to realize this, the Time-based Dithering Algorithm, which varies the pattern of adjacent pixels on every frame, should be used. This is explained in detail. For the 16 gray level, FRC should have the following relationship between gray level and FRC. The 15th gray level should always have pixel-on, and the 14th gray level should have 6 times pixel-on and one times pixel-off, and the 13th gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0th gray level should always have pixel-off as shown in Table 12-2. In Table 12-3, the DP1_2 corresponds to the 7th gray level because it has half the duty cycle from having 2 times pixel-on and 2 times pixel-off. Also, the DP4_7 corresponds to 8th gray level because it has (4/7) duty cycle from having 4 times pixel-on and 3 times pixel-off. Using the same methodology, the DP3_5, DP2_3, DP5_7, DP3_4, DP4_5, and DP6_7 are made to correspond to 9th, 10th, 11th, 12th, 13th, and 14th gray level, respectively. For the gray level from 1st to 6th, the reverse sequence of DP6_7, DP4_5, DP3_4, DP2_3, DP3_5, and DP4_7 should be used; this way, new tables for gray level of 1st to 6th are not needed. The Table 12-7 shows that the same pixel value can not have the same FRC sequence. For example, if the Pi pixel has half gray level in Nth frame, and if adjacent pixel of Pi+1 also has half gray level in Nth frame, and if adjacent pixel of Pi+2 also has half gray level in Nth frame, and if adjacent pixel of Pi+3 also has half gray level in Nth frame, the Pi, Pi+1, Pi+2, and Pi+3 pixel should be 1, 0, 1, and 0 in Nth frame. In (N+1)th frame, the Pi, Pi+1, Pi+2, and Pi+3 pixel should be 0, 1, 0, and 1 as shown in Table 12-3. In case of arbitrary pixel values on arbitrary position, the H/W will select a suitable display value by referring to the corresponding frame number and pixel position. This type of display methodology can randomize the pixel display to reduce the Flicker Noise. The value of table 12-3 is just only reference, and users can specify their own value suitable for the LCD display. Table 12-2. Dither Duty Cycle Examples Pre-dithered Data (Gray Level Number) 15 14 13 12 11 10 9 8 Pixel Duty Rate S3C44B0X has eight programmable registers, such as DP6_7, DP4_5, DP5_7, DP3_4, DP2_3, DP3_5, DP4_7, and Duty Cycle 1 6/7 4/5 3/4 5/7 2/3 3/5 4/7 Pre-dithered Data (Gray Level Number) 7 6 5 4 3 2 1 0 Duty Cycle 1/2 3/7 2/5 1/3 1/4 1/5 1/7 0 12-7 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR DP1_2. The pre-dithered data 1111b has a dithering data '1' because the duty rate is 1. The pre-dithered data 0000b has a dithering data 0 because the duty rate is 0. The pre-dithered data from 0001b to 1110b refer to DP6_7, DP4_5, DP5_7, DP3_4, DP2_3, DP3_5, DP4_7, and DP1_2 registers for dithering data.(The dithering data are used to do FRC.) The DP6_7, DP4_5, DP5_7, DP3_4, DP2_3, DP3_5, DP4_7, and DP1_2, registers can also determine the duty rates, such as 6/7, 4/5, 5/7, 3/4, 2/3, 3/5, and 4/7, respectively. For examples, 1/7 can be made by inverting 6/7. Table 12-3. Recommended Dithering Pattern Pattern Name DP1_2 DP4_7 DP3_5 DP2_3 DP5_7 DP3_4 DP4_5 DP6_7 Number of Bits 16 28 20 12 28 16 20 28 1010 0101 1010 0101 Recommened Pattern (0xA5A5) 1011 1010 0101 1101 1010 0110 0101 (0xBA5DA65) 1010 0101 1010 0101 1111 1101 0110 1011 (0xA5A5F) (0xD6B) 1110 1011 0111 1011 0101 1110 1101 (0xEB7B5ED) 0111 1101 1011 1110 0111 1110 1011 1101 1111 (0x7DBE) (0x7EBDF) 0111 1111 1101 1111 1011 1111 1110 (0x7FDFBFE) 1 1 1 1 5th FRAME 10th FRAME 4th FRAME 9th FRAME 0 1 0 1 . . . 1 0 1 0 3rd FRAME 8th FRAME 2nd FRAME 7th FRAME . . . 0 1 0 1 . . . 1 0 1 0 1st FRAME 6th FRAME 11th FRAME . . . NOTE: This figure is only explanation. The real operation is some different. . . . Figure 12-2. The example of DP3_5 pattern 12-8 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER LCD Self Refresh Mode The LCD controller within S3C44B0X can support the self refresh mode to reduce power comsumption. The self refresh mode can only be applied to only the LCD which has the special LCD driver, for example, LCD panel of SED1580D from Seiko Epson Corporation. The SED1580D has the built-in display memory, which can display the previous stored image in the built-in display memory without image data fetch when the self refresh mode has been invoked. The kind of self refresh mode can be made by writing the control bit of SELFREF in the LCDCON3 register. If the SELFREF bit is set to 1, the LCD controller enters into the self refresh mode from the next line. When the LCD controller enters into the self refresh mode, the signal of VCLK and VD should be fixed as Low and last VD value, but the signal of VM, VFRAME, and VLINE will be generated continuously. To exit the self refresh mode, the user should execute the following path, 1) disable the ENVID bit in LCDCON 1 register , 2) disable SELFREF bit in LCDCON 3 register and 3) enable ENVID bit again in LCDCON 1 register. SL_IDLE Mode (LCD dedicated Idle Mode) The SL_IDLE mode in the power management scheme should be used to enter into the LCD driver's self refresh mode. In SL_IDLE mode, all function blocks except the LCD controller within S3C44B0X should be stopped to reduce the power comsumption, because the power management block inserts divide_by_n input clock only to the LCD controller. Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted to display the line on the panel. The VM signal provides an AC signal for the display. It is used by the LCD to alternate the polarity of the row and column voltages, used to turn the pixels on and off, because the LCD plasma tends to deteriorate whenever subjected to a DC voltage. It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals. Figure 12-3 shows the timing requirements for the LCD driver interface. 12-9 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR Full Frame Timing, MMODE = 0 VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 Full Frame Timing, MMODE = 1 VFRAME VM VLINE LINE1LINE2LINE3LINE4LINE5LINE6 LINEnLINE1 LINEnLINE1 First Line Timing VFRAME VM VLINE LINECNT VCLK WDLY First Line Check & Data Timing VFRAME VM VLINE VCLK VD[7:0] WDLY WLH LINEBLANK WDLY Display the last line of the previous frame LINECNT decreases & Display the 1st line Figure 12-3. 8-bit Single Scan Display Type LCD Timing 12-10 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 12-4 shows these 3 different display types for monochrome displays, and figure 12-5 shows these 3 different display types for color displays. 4-bit dual scan display type A 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time. The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half, as shown in figure 12-4. The end of frame is reached when each half of the display has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 4-bit single scan display type A 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 4 pins(VD[3:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver, and the 4 pins(VD[7:4]) for the LCD output are not used. 8-bit single scan display type An 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. Color displays Color displays require 3 bits (Red, Green, Blue) of image data per pixel, resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line. This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. Figure 12-5 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays. 12-11 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4 . . . . . . 4-bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . 4-bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 . . . . . . 8-bit Single Scan Display Figure 12-4. Monochrome Display Types 12-12 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel . . . . . . VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4 R1 G1 B1 R2 G2 B2 R3 G3 . . . . . . 4-bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel . . . . . . 4-bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel . . . . . . 8-bit Single Scan Display Figure 12-5. Color Display Types 12-13 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR MEMORY DATA FORMAT (BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address 0000H 0004H * * * LCD Panel A[31] A[30] ...... A[0] B[31] B[30] ...... B[0] ...... Data A[31:0] B[31:0] L[31] L[30] ...... L[0] M[31] M[30] ...... M[0] ...... 1000H 1004H * L[31:0] M[31:0] * * LCD Panel A[31] A[30] A[29] ...... A[0] B[31] B[30] ...... B[0] C[31] ...... C[0] ...... Mono 4-bit Single Scan Display & 8-bit Single Scan Display: Video Buffer Memory: Address 0000H 0004H 0008H * * * Data A[31:0] B[31:0] C[31:0] In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In color mode, 8 bits (3 bits of red, 3 bits of green, 2 bits of blue) of video data correspond to 1 pixel. The color data format in a byte is as follows; Bit [ 7:5 ] Red Bit [ 4:2 ] Green Bit[1:0] Blue 12-14 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY The S3C44B0X supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed(refer to Fig. 12-6) but not the values of PAGEWIDTH and OFFSIZE. The size of video buffer in which the image is stored should be larger than LCD panel screen size. PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. LCDBASEU View Port (The same size of LCD panel) LINEVAL + 1 LCDBASEL This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. Figure 12-6. Example of Scrolling in Virtual Display(single scan) . . . . . . Before Scrolling After Scrolling 12-15 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register LCDCON1 Address 0x01F00000 R/W R/W Description LCD control 1 register Reset Value 0x00000000 LCDCON1 LINECNT (read only) CLKVAL Bit [31:22] [21:12] Description These bits provide the status of the line counter. Down count from LINEVAL to 0 These bits determine the rate of VCLK. If this value can be changed when ENVID=1, the new value will be used next frame. VCLK = MCLK / (CLKVAL x 2) ( CLKVAL 2 ) These bits determine the VLINE pulse's high level width by counting the number of the system clock. 00 = 4 clock, 01 = 8 clock, 10 = 12 clock, 11 = 16 clock These bits determine the delay between VLINE and VCLK by counting the number of the system clock 00 = 4clock, 01 = 8 clock, 10 = 12 clock, 11 = 16 clock This bit determines the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL These bits select the display mode. 00 = 4-bit dual scan display mode 01 = 4-bit single scan display mode 10 = 8-bit single scan display mode 11 = Not used This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge This bit indicates the line pulse polarity. 0 = normal 1 = inverted This bit indicates the frame pulse polarity. 0 = normal 1 = inverted This bit indicates the video data(VD[7:0]) polarity. 0 = Normal 1 = VD[7:0] output is inverted. LCD video output and the logic enable/disable. 0 = Disable the video output and the logic. The LCD FIFO is cleared. 1 = Enable the video output and the logic. Initial State 0000000000 0000000000 WLH [11:10] 00 WDLY [9:8] 00 MMODE DISMODE [7] [6:5] 0 00 INVCLK [4] 0 INVLINE INVFRAME INVVD [3] [2] [1] 0 0 0 ENVID [0] 0 12-16 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER LCD Control 2 Register Register LCDCON2 Address 0x01F00004 R/W R/W Description LCD control 2 register Reset Value 0x00000000 LCDCON2 LINEBLANK Bit [31:21] Description These bits indicate the blank time in one horizontal line duration time. These bits adjust the rate of the VLINE finely. The unit of LINEBLANK is MCLK. Ex) If the value of LINEBLANK is 10, the blank time is inserted to VCLK during 10 system clocks. Initial State 0x000 HOZVAL [20:10] These bits determine the horizontal size of the LCD panel. HOZVAL has to be determined to meet the condition that total bytes of 1 line be 2n bytes. If the x size of LCD is 120 dots in mono mode, x=120 can not be supported because 1 line consists of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line consists of 16 bytes(2n). The additional 8 dot will be discarded by LCD panel driver. 0x000 LINEVAL [9:0] These bits determine the vertical size of LCD panel. 0x000 LCD Control 3 Register Register LCDCON3 Address 0x01F00040 R/W R/W Description Test Mode Enable Register Reset Value 0x00 LCDCON3 Reserved SELFREF Bit [2:1] [0] reserved for test Description initial state 0 0 LCD self refresh mode enable bit 0 : LCD self refresh mode disable 1 : LCD self refresh mode enable 12-17 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR FRAME Buffer Start Address 1 Register Register LCDSADDR1 Address 0x01F00008 R/W R/W Description Frame buffer start address 1 register Reset Value 0x000000 LCDSADDR1 MODESEL Bit [28:27] Description These bits select the monochrome, gray, or color mode. 00 = monochrome mode 01 = 4-level gray mode 10 = 16-level gray mode 11 = color mode These bits indicate A[27:22] of the bank location for the video buffer in the system memory. LCDBANK value can not be changed even when moving the view port. LCD frame buffer should be inside aligned 4MB region, which ensures that LCDBANK value should not be changed when moving the view port. So, using the malloc function the care should be taken. These bits indicate A[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD. Initial State 00 LCDBANK [26:21] 0x00 LCDBASEU [20:0] 0x000000 NOTES: 1. LCDBANK can't be changed while ENVID=1 2. If LCDBASEU,LCDBASEL is changed during ENVID=1, the new value will be used next frame. If you use serveral frame buffer for better display quality and if you write the previous frame memory just after changing LCDBASEU,LCDBASEL, the items drawn on the previous frame memory may be shown. To avoid th is undesirable phenomen, you may have to check LINECNT. 12-18 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER FRAME Buffer Start Address 2 Register Register LCDSADDR2 Address 0x01F0000C R/W R/W Description Frame buffer start address 2 register Reset Value 0x000000 LCDSADDR2 BSWP Bit [29] Byte swap control bit 1 : Swap Enable Description 0 : Swap Disable Initial State 0 LCD DMA fetches the frame memory data by 4 word burst access. In little endian mode and BSWP is 0, the frame memory data are displayed in the sequence, 4n+3th, 4n+2th ,4n+1th ,4nth data. If BSWP is 1, the sequence will be 4n-th, 4n+1th, 4n+2th, 4n+3th. If the CPU is little endian mode, the frame buffer may be accessed by only byte access mode, Because BSWP is 1, the byte accessed data will be shown correctly also in the little endian mode. In the other case, BSWP has to be 0. MVAL LCDBASEL [28:21] [20:0] These bits define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. These bits indicate A[21:1] of the start address of the lower address counter, which is used for the lower frame memory of dual scan LCD. LCDBASEL = LCDBASEU + (PAGEWIDTH + OFFSIZE) x (LINEVAL +1) NOTE: users Users can change the LCDBASEU and LCDBASEL values for scrolling while LCD controller is turned on. But, must not change the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register. Because of the LCD FIFO fetches the next frame data prior to the change in the frame. So, if you change the frame, the pre-fetched FIFO data will be obsolete and LCD controller will display the incorrect screen. To check the LINECNT, interrutpt should be masked. If any interrupt is executed just after reading LINECNT, the read LINECNT value may be obsolete because of the execution time of ISR(interrupt service routine). 0x00 0x0000 12-19 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR FRAME Buffer Start Address 3 Register Register LCDSADDR3 Address 0x01F00010 R/W R/W Description Virtual screen address set Reset Value 0x000000 LCDSADDR3 OFFSIZE Bit [19:9] Description Virtual screen offset size(the number of half words) This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line. Virtual screen page width(the number of half words) This value defines the width of the view port in the frame Initial State 0x0000 PAGEWIDTH NOTE: [8:0] 0x000 The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0. Example 1. LCD panel = 320*240, 16gray, single scan frame start address = 0xc500000 offset dot number = 2048 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320*4/16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0xc500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) * ( 0xef + 1 ) = 0xa2b00 Example 2. LCD panel = 320*240, 16gray, dual scan frame start address = 0xc500000 offset dot number = 2048 dots ( 512 half words ) LINEVAL = 120-1 = 0x77 PAGEWIDTH = 320*4/16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0xc500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) * ( 0x77 + 1 ) = 0x91580 Example 3. LCD panel = 320*240, color, single scan frame start address = 0xc500000 offset dot number = 1024 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320*8/16 = 0xa0 OFFSIZE = 512 = 0x200 LCDBANK = 0xc500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0xa0 + 0x200 ) * ( 0xef + 1 ) = 0xa7600 12-20 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER RED Lookup Table Register Register REDLUT Address 0x01F00014 R/W R/W Description Red lookup table register Reset Value 0x00000000 REDLUT REDVAL Bit [31:0] Description These bits define which of the 16 shades each of the 8 possible red combinations will choose. 000 = REDVAL[3:0], 001 = REDVAL[7:4] 010 = REDVAL[11:8], 011 = REDVAL[15:12] 100 = REDVAL[19:16], 101 = REDVAL[23:20] 110 = REDVAL[27:24], 111 = REDVAL[31:28] Initial State 0x00000000 GREEN Lookup Table Register Register GREENLUT Address 0x01F00018 R/W R/W Description Green lookup table register Reset Value 0x00000000 GREENLUT GREENVAL Bit [31:0] Description These bits define which of the 16 shades each of the 8 possible green combinations will choose. 000 010 100 110 = = = = GREENVAL[3:0], GREENVAL[11:8], GREENVAL[19:16], GREENVAL[27:24], 001 011 101 111 = GREENVAL[7:4] = GREENVAL[15:12] = GREENVAL[23:20] = GREENVAL[31:28] Initial State 0x00000000 BLUE Lookup Table Register Register BLUELUT Address 0x01F0001C R/W R/W Description Blue lookup table register Reset Value 0x0000 BULELUT BLUEVAL Bit [15:0] Description These bits define which of the 16 shades each of the 4 possible blue combinations will choose 00 = BLUEVAL[3:0], 01 = BLUEVAL[7:4] 10 = BLUEVAL[11:8], 11 = BLUEVAL[15:12] Initial State 0x0000 12-21 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR Dithering Pattern DP1_2 Register Register DP1_2 Address 0x01F00020 R/W R/W Description Dithering pattern duty 1/2 register ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0xa5a5 DP1_2 DP1_2 Bit [15:0] Description Recommended pattern value 1010 0101 1010 0101 (0xa5a5) Initial state 0xa5a5 Dithering Pattern DP4_7 Register Register DP4_7 Address 0x01F00024 R/W R/W Description Dithering pattern duty 4/7 register ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0xba5da65 DP4_7 DP4_7 Bit [27:0] Description Recommended pattern value 1011 1010 0101 1101 1010 0110 0101 (0xba5da65) Initial state 0xba5da65 Dithering Pattern DP3_5 Register Register DP3_5 Address 0x01F00028 R/W R/W Description Dithering pattern duty 3/5 register ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0xa5a5f DP3_5 DP3_5 Bit [19:0] Description Recommended pattern value 1010 0101 1010 0101 1111 (0xa5a5f) Initial state 0xa5a5f 12-22 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER Dithering Pattern DP2_3 Register Register DP2_3 Address 0x01F0002C R/W R/W Description Dithering pattern duty 2/3 register (Please, refer to a sample program source for the latest value of this register). Reset Value 0xd6b DP2_3 DP2_3 Bit [11:0] Description Recommended pattern value 1101 0110 1011 (0xd6b) Initial state 0xd6b Dithering Pattern DP5_7 Register Register DP5_7 Address 0x01F00030 R/W R/W Description Dithering pattern duty 5/7 register (Please, refer to a sample program source for the latest value of this register). Reset Value 0xeb7b5ed DP5_7 DP5_7 Bit [27:0] Description Recommended pattern value 1110 1011 0111 1011 0101 1110 1101 (0xeb7b5ed) Initial state 0xeb7b5ed Dithering Pattern DP3_4 Register Register DP3_4 Address 0x01F00034 R/W R/W Description Dithering pattern duty 3/4 register ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0x7dbe DP3_4 DP3_4 Bit [15:0] Description Recommended pattern value 0111 1101 1011 1110 (0x7dbe) Initial state 0x7dbe 12-23 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR Dithering Pattern DP4_5 Register Register DP4_5 Address 0x01F00038 R/W R/W Description Dithering pattern duty 4/5 register ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0x7ebdf DP4_5 DP4_5 Bit [19:0] Description Recommended pattern value 0111 1110 1011 1101 1111 (0x7ebdf) Initial state 0x7ebdf Dithering Pattern DP6_7 Register Register DP6_7 Address 0x01F0003C R/W R/W Description Dithering pattern duty 6/7 register ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0x7fdfbfe DP6_7 DP6_7 Bit [27:0] Description Recommended pattern value 0111 1111 1101 1111 1011 1111 1110 (0x7fdfbfe) initial state 0x7fdfbfe Dithering Mode Register Register DITHMODE Address 0x01F00044 R/W R/W Description Dithering Mode Register. This register reset value is 0x00000. But, users will have to change this value to 0x12210. ( Please, refer to a sample program source for the latest value of this register ). Reset Value 0x00000 DP8_9 DITHMODE Bit [18:0] Description Use one of following value for your LCD 0x12210 or 0x0 initial state 0x00000 12-24 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER Register Setting Guide The maximum VCLK frequency of the LCD controller is 16.5MHz whenever system clock frequency is 66 MHz; therefore the LCD controller supports all existing LCD drivers. The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. The data transmission rate for the VD port of the LCD controller should be calculated, in order to determine the value of CLKVAL register. The data transmission rate is given by the following equation: CLKVAL has to be determined, such that the VCLK value is greater than the data transmission rate. Data transmission rate = HS x VS x FR x MV HS: Horizontal LCD size VS: Vertical LCD size FR: Frame rate MV: Mode dependent value Table 12-4. MV Value for Each Display Mode Mode Mono, 4-bit single scan display Mono, 8-bit single scan display or 4-bit dual scan display 4 level gray, 4-bit single scan display 4 level gray, 8-bit single scan display or 4-bit dual scan display 16 level gray, 4-bit single scan display 16 level gray, 8-bit single scan display or 4-bit dual scan display Color, 4-bit single scan display Color, 8-bit single scan display or 4-bit dual scan display MV Value 1/4 1/8 1/4 1/8 1/4 1/8 3/4 3/8 12-25 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR The LCDBASEU register value is the first address value of the frame buffer. The lowest 4 bits must be eliminated for burst 4 word access. The LCDBASEL register value is determined by LCD size and LCDBASEU. The LCDBASEL value is given by the following equation: LCDBASEL = LCDBASEU + LCDBASEL offset Example 1: 160 x 160pixel, 4-level gray, 80 frame/sec, 4-bit single scan display, system clock frequency = 66 MHz, WLH = 1, WDLY = 1, LCD frame buffer = SDRAM, Bus width = 16bit. System bus occupation = (LCD data transmission frequency) / (System clock frequency) LCD data transmission frequency = (Total LCD data during 1sec) x (Transmission cycle / 1byte) Total LCD data during 1sec = Total LCD data x frame rate = 160 x 160pixel x (2bit / 1pixel) x 80Hz x (1byte / 8bit) = 512Kbyte Transmission cycle per 1byte = Transmission clock per 4word / 16 Transmission clock per 4word = Trp(=2clk) + Trcd(=2clk) + C/L(=2clk) + Burst cycle(=8clk) = 14clk System load (system bus occupation) : 448KHz / 66MHz = 0.68% NOTE: The higher the system load is, the lower the CPU performance is. Example 2 (Virtual screen register) : 4 -level gray, 4-bit single scan display, Vertual screen size = 1024 x 1024, LCD size = 320 x 240, LCDBASEU = 0x64. 1 half-word = 8 pixels(4-level gray), Virtual screen 1 line = 128 half-word = 1024 pixels, LCD 1 line = 320 pixels = 40 half-word, OFFSIZE = 128 - 40 = 88 = 0x58, PAGEWIDTH = 40 = 0x28 LCDBASEL = LCDBASEU + (PAGEWIDTH + OFFSIZE) x (LINEVAL +1) = 100 + (40 +88) x 240 = 0x3C64 12-26 S3C44B0X RISC MICROPROCESSOR LCD CONTROLLER Gray Level Selection Guide S3C44B0X LCD controller can generate 16 gray level using FRC(frame rate control). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erronous patterns may be shown in fast response LCD or at lower frame rates. Because the quality of LCD gray levels depends on LCD's own characteristics, the user may have to select the good gray levels after viewing all gray levels on user's own LCD. Please select the gray level quality through the following procedures. 1. Get the latest dithering pattern register value from SAMSUNG. 2. Display 16gray bar in LCD. 3. Change the frame rate into an optimal value. 4. Change the VM alternating period to get the best quality. 5. If some gray level quality is not good, select the good gray levels, which is displayed well on your LCD. 12-27 LCD CONTROLLER S3C44B0X RISC MICROPROCESSOR NOTES 12-28 S3C44B0X RISC MICROPROCESSOR A/D CONVERTER 13 OVERVIEW FEATURES -- -- -- -- -- -- -- Resolution: 10-bit A/D CONVERTER The 10-bit CMOS ADC(Analog to Digital Converter) of S3C44B0X consists of a 8-channel analog input multiplexer, auto-zeroing comparator, clock generator, 10 bit successive approximation register (SAR), and output register. This ADC provides software-selection power-down(sleep) mode. Differential Linearity Error: 1 LSB Integral Linearity Error: 2 LSB ( Max. 3 LSB) Maximum Conversion Rate: Input voltage range: 0-2.5V Input bandwidth: 0-100 Hz (without S/H(sample&hold) circuit) Low Power Consumption 100 KSPS 13-1 A/D CONVERTER S3C44B0X RISC MICROPROCESSOR A/D CONVERTER OPERATION BLOCK DIAGRAM Figure 13-1 shows the functional block diagram of S3C440BX A/D converter. Note that the reference positive voltage REFT and reference negative voltage RETB are applied internally by A/D converter power supply and ground, so no power is applied to REFT and REFB pins. Also REFT, REFB, and analog common voltage VCOM should be connected to bypass capacitors respectively because of voltage level stability. AMUX 8 DAC VCOM CTRL + COMP SAR INT ADCINT AIN[7:0] MCLK PSR ADCDAT 10 Data Bus Figure 13-1. A/D Converter Block Diagram FUNCTION DESCRIPTIONS SAR (Successive Approximation Register) A/D Converter Operation A SAR type A/D converter basically consists of the comparator, D/A converter, and SAR logic. At the beginning of the conversion, the MSB is switched ON and the analog input signal is compared the reference signal of D/A converter. Because the A/D converter was designed with differential architecture, D/A converter generates the differential reference signal internally and the two difference signals - one signal is the difference between analog input and positive reference signal, the other is between the analog common voltage(VCOM) and negative reference signal - are delivered to comparator. The comparator then compares the analog input with the reference signal differentially. When the input signal is larger than the reference, then MSB remains ON and the next bit is switched ON and a comparison will be performed. A bit by bit operation is in this system bring the reference signal within 1 LSB of the time discrete input signal. A/D Conversion Time When the system clock frequency is 66MHz and the prescaler value is 20, total 10-bit conversion time is as follows. 66 MHz / 2(20+1) / 16(at least 16 cycle by 10-bit operation) = 98.2 KHz = 10.2 us NOTE: Because this A/D converter has no sample-and-hold circuit, analog input frequency should not exceed 100Hz for accurate conversion although the maximum conversion rate is 100KSPS. 13-2 S3C44B0X RISC MICROPROCESSOR A/D CONVERTER Sleep Mode The ADC sleep mode is activated by setting the SLEEP bit, ADCCON[5], to '1'. In this mode, the conversion clock is disabled and A/D conversion operation is halted. The A/D converter data register contains the previous data in sleep mode. NOTE: After the ADC exits the sleep mode(ADCCON[5]=1? 0 ), there is 10ms wait for the ADC reference voltage stabilization before the first AD conversion. ADC reference pin configuration Users must configure S3C44B0X's reference pins(83, 84, 85) as shown in Fig.13-2. AVCOM 10nF AREFT 10nF AREFB 10nF Figure 13-2. External reference pin configuration Workaround For the ADC Data Reading Problem The ADC converter state flag(ADCCON[6], FLAG bit) is not correct. The FLAG operates incorrectly in the following cases: a) The FLAG will be 1 for one ADC clock time just after the ADC conversion is started. This is not correct. b) The FLAG will be 1 one ADC clock time ago than the ADC conversion is completed. This is not correct. This problem will be shown conspicuously only if the ADCPSR is large. To read ADC converted data correctly , please refer to the following codes; rADCCON=0x1|(0x0<<2); while(rADCCON &0x1); //Start A/D conversion //To avoid The first FLAG error case. //(The START bit is cleared in one ADC clock.) while(!(rADCCON & 0x40)); for(i=0;i A/D CONVERTER S3C44B0X RISC MICROPROCESSOR The Programming Technique in ADC 1. There is no sample & hold circuit on the ADC input pin. So, The small current will flow in/out from AINn input pins because of the ADC internal operation. If the output impedance of source signal is high, this current will change the signal voltage. The current is about 7.6uA in the following condition. Condition Induced Current Induced ADC Error 100KSPS, 10K-ohm resister, Vsource=0.0V 7.8uA (78mV) 32 1) This ADC error will be decreased if the output impedance of the signal source is reduced. For example, If the output impedance of the signal source is 1Kohm, the induced ADC error by the ADC input current is 3(1/10). 2) The current will be also decreased if ADCPSR is large. If the ADC conversion rate is 30KSPS, the current will be about 1.2uA. The ADCPSR value is higher, the current is lower. 2. 3. The ADC conversion error is decreased if the ADCPSR is large beside the above ADC conversion error. If you want accurate ADC conversion, you let the ADCPSR as large as possible. Because our ADC have no sample&hold circuit, the input frequency bandwidth is 0~100Hz. This limitation is because there is no internal sample&hold circuit. But, If you can ignore the small ADC error(or an external S/H circuit is used), the higher frequency signal can be converted. If the ADC channel is changed, the channel setup time(min. 15us) is needed. So, If the ADC channel is changed, you must wait for 15us and then start AD conversion. After the ADC exits the sleep mode(the initial state is the sleep mode), there is 10ms wait for the ADC reference voltage stabilization before the first AD conversion. Our ADC has ADC start-by-read feature. This feature can be used for DMA to move the ADC data to memory. If you read the ADCDAT by polling method, you must apply the work-around for ADC data reading problem. 4. 5. 6. 7. 13-4 S3C44B0X RISC MICROPROCESSOR A/D CONVERTER A/D CONVERTER SPECIAL REGISTERS A/D CONVERTER CONTROL REGISTER (ADCCON) Register ADCCON Address 0x01D40000(Li/W, Li/HW, Li/B, Bi/W) 0x01D40002(Bi/HW) 0x01D40003(Bi/B) R/W R/W Description A/D Converter control Register Reset Value 0x20 ADCCON FLAG Bit [6] Description A/D converter state flag (Read Only). 0 = A/D conversion in process 1 = End of A/D conversion If check this bit please refer to workaround in page13-3. System power down 0 = Normal operation, 1 = Sleep mode Clock source select 000 = AIN0 001 = AIN1 010 = AIN2 011 = AIN3 100 = AIN4 101 = AIN5 110 = AIN6 111 = AIN7 A/D conversion start by read 0 = Disable start by read operation 1 = Enable start by read operation A/D conversion start by enable. If READ_START is enabled, this value is not valid. 0 = No operation 1 = A/D conversion starts and this bit is cleared after the start-up. Initial State 0 SLEEP INPUT SELECT READ_ START [5] [4:2] 1 00 [1] 00 ENABLE_START [0] 0 NOTES: 1. The ADCCON register can be accessed by halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in the Little/Big endian mode. 2. (Li/B/HW/W): Access by char/halfword/word unit when the endian mode is Little. (Bi/B/HW/W): Access by char/halfword/word unit when the endian mode is Big. 13-5 A/D CONVERTER S3C44B0X RISC MICROPROCESSOR A/D CONVERTER PRESCALER REGISTER (ADCPSR) Register ADCPSR Address 0x01D40004(Li/W, Li/HW, Li/B, Bi/W) 0x01D40006(Bi/HW) 0x01D40007(Bi/B) R/W R/W Description A/D Converter prescaler Register Reset Value 0x0 ADCPSR PRESCALER Bit [7:0] Description Prescaler value (0-255) Division factor = 2 (prescaler_value+1). Total clocks for ADC converstion = 2*(Prescalser_value+1)*16 Initial State 0 NOTES: 1. The ADCPSR register can be accessed by halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by char/halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by char/halfword/word unit when the endian mode is Big. A/D CONVERTER DATA REGISTER (ADCDAT) After A/D conversion is completed, the ADCDAT reads the converted data. ADCDAT has to be read after the conversion has been completed. Register ADCDAT Address 0x01D40008(Li/W, L/HW, Bi/W) 0x01D4000A(Bi/HW) R/W R Description A/D converter data register Reset Value - ADCDAT ADCDAT Bit [9:0] Description A/D converter output data value Initial State - NOTES: 1. The ADCDAT register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big. 13-6 S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK 14 OVERVIEW FEATURES -- -- -- -- -- -- -- RTC (REAL TIME CLOCK) The RTC (Real Time Clock) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as BCD (Binary Coded Decimal) values using the STRB/LDRB ARM operation. The data include second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 KHz crystal and also can perform the alarm function. BCD number: second, minute, hour, date, day, month, year Leap year generator Alarm function: alarm interrupt or wake-up from power down mode. Year 2000 problem is removed. Independent power pin (VDDRTC) Supports millisecond tick time interrupt for RTOS kernel time tick. Round reset function 14-1 REAL TIME CLOCK S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK OPERATION TICNT Time Tick Generator 128 Hz 215 Clock Divider RTCRST Reset Register Leap Year Generator TIME TICK XTAL 1Hz SEC EXTAL MIN HOUR DATE DAY MON YEAR Control Register RTCCON PMWKUP Alarm Generator RTCALM PWDN ALMINT Figure 14-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR This block can determine whether the last date of each month is 28, 29, 30, or 31, based on data from BCDDAY, BCDMON, and BCDYEAR. This block considers the leap year in deciding on the last date. An 8-bit counter can only represent 2 BCD digits, so it cannot decide whether 00 year is a leap year or not. For example, it can not discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C44B0X has hard-wired logic to support the leap year in 2000. Please note 1900 is not leap year while 2000 is leap year. Therefore, two digits of 00 in S3C44B0X denote 2000, not 1900. READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set in order to read and write the register in RTC block. To display the sec., min., hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block. However, a one second deviation may exist because multiple registers are read. For example, when the user reads the registers from BCDYEAR to BCDMIN, the result is assumed to be 1959(Year), 12(Month), 31(Date), 23(Hour) and 59(Minute). When the user read the BCDSEC register and the result is a value from 1 to 59(Second), there is no problem, but, if the result is 0 sec., the year, month, date, hour, and minute may be changed to 1960(Year), 1(Month), 1(Date), 0(Hour) and 0(Minute) because of the one second deviation that was mentioned. In this case, user should re-read from BCDYEAR to BCDSEC if BCDSEC is zero. BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery, which supplies the power through the RTCVDD pin into RTC block, even if the system power is off. When the system off, the interfaces of the CPU and RTC logic should be blocked, and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation. 14-2 S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power down mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated. In the power down mode the power management wakeup (PMWKUP) signal is activated as well as the ALMINT. The RTC alarm register, RTCALM, determines the alarm enable/disable and the condition of the alarm time setting. TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches '0' when the tick time interrupt occurs. Then the period of interrupt is as follow: Period = ( n+1 ) / 128 second n : Tick time count value (1-127) This RTC time tick may be used for RTOS(real time operating system) kernel time tick. If time tick is generated by RTC time tick, the time related function of RTOS will always synchronized with real time. ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register, RTCRST. The round boundary (30, 40, or 50 sec) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. For example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. NOTE All RTC registers have to be accessed by the byte unit using the STRB,LDRB instructions or char type pointer. 32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 14-2 is an example circuit of the RTC unit oscillation at 32.768Khz. 15-22 pF XTAL1 32,768 Hz EXTAL1 Figure 14-2. Main Oscillator Circuit Examples 14-3 REAL TIME CLOCK S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL REGISTER (RTCCON) The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset. Also before power off, the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers. Register RTCCON Address 0x01D70040(L) 0x01D70043(B) R/W Description Reset Value 0x0 R/W RTC control Register (by byte) RTCCON CLKRST CNTSEL Bit [3] [2] Description RTC clock count reset 0 = No reset, 1 = Reset BCD count select 0 = Merge BCD counters 1 = Reserved (Separate BCD counters) BCD clock select 0 = XTAL 1/215 divided clock 1 = Reserved (XTAL clock only for test) RTC read/write enable 0 = Disable, 1 = Enable If RTC read/write feature is enabled, The STOP current will be consumed excessively. To reduce STOP current, this bit should be 0 while not accessing RTC. Although this bit is 0, the RTC clock is still alive. Initial State 0 0 CLKSEL [1] 0 RTCEN [0] 0 NOTES: 1. All RTC registers have to be accessed by byte unit using STRB and LDRB instructions or char type pointer. 2. (L): When the endian mode is little endian. (B): When the endian mode is Big endian. 14-4 S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK RTC ALARM CONTROL REGISTER (RTCALM) RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode. Register RTCALM Address 0x01D70050(L) 0x01D70053(B) R/W Description Reset Value 0x00 R/W RTC alarm control Register (by byte) RTCALM Reserved ALMEN YEAREN MONREN DAYEN HOUREN MINEN SECEN Bit [7] [6] [5] [4] [3] [2] [1] [0] Description Initial State 0 Alarm global enable 0 = Disable, 1 = Enable Year alarm enable 0 = Disable, 1 = Enable Month alarm enable 0 = Disable, 1 = Enable Day alarm enable 0 = Disable, 1 = Enable Hour alarm enable 0 = Disable, 1 = Enable Minute alarm enable 0 = Disable, 1 = Enable Second alarm enable 0 = Disable, 1 = Enable 0 0 0 0 0 0 0 14-5 REAL TIME CLOCK S3C44B0X RISC MICROPROCESSOR ALARM SECOND DATA REGISTER (ALMSEC) Register ALMSEC Address 0x01D70054(L) 0x01D70057(B) R/W Description Reset Value 0x00 R/W Alarm second data Register (by byte) ALMSEC Reserved SECDATA Bit [7] [6:4] [3:0] Description Initial State 0 BCD value for alarm second from 0 to 5 from 0 to 9 000 0000 ALARM MIN DATA REGISTER (ALMMIN) Register ALMMIN Address 0x01D70058(L) 0x01D7005B(B) R/W Description Reset Value 0x00 R/W Alarm minute data Register (by byte) ALMMIN Reserved MINDATA Bit [7] [6:4] [3:0] Description Initial State 0 BCD value for alarm minute from 0 to 5 from 0 to 9 000 0000 ALARM HOUR DATA REGISTER (ALMHOUR) Register ALMHOUR Address 0x01D7005C(L) 0x01D7005F(B) R/W Description Reset Value 0x00 R/W Alarm hour data Register (by byte) ALMHOUR Reserved HOURDATA Bit [7:6] [5:4] [3:0] Description Initial State 0 BCD value for alarm hour from 0 to 2 from 0 to 9 00 0000 14-6 S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK ALARM DAY DATA REGISTER (ALMDAY) Register ALMDAY Address 0x01D70060(L) 0x01D70063(B) R/W Description Reset Value 0x01 R/W Alarm day data Register (by byte) ALMDAY Reserved DAYDATA Bit [7:6] [5:4] [3:0] Description Initial State 0 BCD value for alarm day, from 0 to 28, 29, 30, 31 from 0 to 3 from 0 to 9 00 0001 ALARM MON DATA REGISTER (ALMMON) Register ALMMON Address 0x01D70064(L) 0x01D70067(B) R/W Description Reset Value 0x01 R/W Alarm month data Register (by byte) ALMMON Reserved MONDATA Bit [7:5] [4] [3:0] Description Initial State 0 BCD value for alarm month from 0 to 1 from 0 to 9 0 0001 ALARM YEAR DATA REGISTER (ALMYEAR) Register ALMYEAR Address 0x01D70068(L) 0x01D7006B(B) R/W Description Reset Value 0x00 R/W Alarm year data Register (by byte) ALMYEAR YEARDATA Bit [7:0] BCD value for year from 00 to 99 Description Initial State 0x00 14-7 REAL TIME CLOCK S3C44B0X RISC MICROPROCESSOR RTC ROUND RESET REGISTER (RTCRST) Register RTCRST Address 0x01D7006C(L) 0x01D7006F(B) R/W Description Reset Value 0x0. R/W RTC round reset Register (by byte) RTCRST SRSTEN SECCR Bit [3] [2:0] Description Round second reset enable 0 = Disable, 1 = Enable Round boundary for second carry generation. (note) 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec Initial State 0 00 NOTE: Otherwise, no second carry is generated. BCD SECOND REGISTER (BCDSEC) Register BCDSEC Address 0x01D70070(L) 0x01D70073(B) R/W Description Reset Value Undef. R/W BCD second Register (by byte) BCDSEC Reserved SECDATA Bit [7] [6:4] [3:0] BCD value for second from 0 to 5 from 0 to 9 Description Initial State - - - BCD MINUTE REGISTER (BCDMIN) Register BCDMIN Address 0x01D70074(L) 0x01D70077(B) R/W Description Reset Value Undef. R/W BCD minute Register (by byte) BCDMIN Reserved MINDATA Bit [7] [6:4] [3:0] BCD value for minute from 0 to 5 from 0 to 9 Description Initial State - - - 14-8 S3C44B0X RISC MICROPROCESSOR REAL TIME CLOCK BCD HOUR REGISTER (BCDHOUR) Register BCDHOUR Address 0x01D70078(L) 0x01D7007B(B) R/W R/W BCD hour Register (by byte) Description Reset Value Undef. BCDHOUR Reserved HOURDATA Bit [7:6] [5:4] [3:0] BCD value for hour from 0 to 2 from 0 to 9 Description Initial State - - - BCD DAY REGISTER (BCDDAY) Register BCDDAY Address 0x01D7007C(L) 0x01D7007F(B) R/W R/W BCD day Register (by byte) Description Reset Value Undef BCDDAY Reserved DAYDATA Bit [7:6] [5:4] [3:0] BCD value for day from 0 to 3 from 0 to 9 Description Initial State - - - BCD DATE REGISTER (BCDDATE) Register BCDDATE Address 0x01D70080(L) 0x01D70083(B) R/W R/W BCD date Register (by byte) Description Reset Value Undef. BCDDATE Reserved DATEDATA Bit [7:3] [2:0] BCD value for date from 1 to 7 Description Initial State - - 14-9 REAL TIME CLOCK S3C44B0X RISC MICROPROCESSOR BCD MONTH REGISTER (BCDMON) Register BCDMON Address 0x01D70084(L) 0x01D70087(B) R/W Description Reset Value Undef. R/W BCD month Register (by byte) BCDMON Reserved MONDATA Bit [7:5] [4] [3:0] BCD value for month from 0 to 1 from 0 to 9 Description Initial State - - - BCD YEAR REGISTER (BCDYEAR) Register BCDYEAR Address 0x01D70088(L) 0x01D7008B(B) R/W R/W BCD year Register (by byte) Description Reset Value Undef. BCDYEAR YEARDATA Bit [7:0] BCD value for year from 00 to 99 Description Initial State - TICK TIME COUNT REGISTER (TICNT) Register TICNT Address 0x01D7008C(L) 0x01D7008F(B) R/W Description Reset Value 0x00000000 R/W Tick time count Register (by byte) TICNT TICK INT ENABLE TICK TIME COUNT Bit [7] [6:0] Description Tick time interrupt enable 0 = disable 1 = enable Tick time count value. (1-127) This counter value decreases internally, and users can not read this real counter value in working. Initial State 0 000000 14-10 S3C44B0X RISC MICROPROCESSOR WATCHDOG TIMER 15 OVERVIEW FEATURES -- -- WATCHDOG TIMER The S3C44B0X watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 MCLK cycles. Normal interval timer mode with interrupt request Internal reset signal is activated for 128 MCLK cycles when the timer count value reaches 0 (time-out). 15-1 WATCHDOG TIMER S3C44B0X RISC MICROPROCESSOR WATCHDOG TIMER OPERATION The functional block diagram of the watchdog timer is shown in Figure 15-1. The watchdog timer uses MCLK as its only source clock. To generate the corresponding watchdog timer clock, the MCLK frequency is prescaled first, and the resulting frequency is divided again. MUX 1/16 1/32 MCLK 8-bit Prescaler 1/64 1/128 WTDAT Interrupt WTCNT (Down Counter) Reset Signal Generator RESET WTCON[15:8] WTCON[4:3] WTCON[2] WTCON[0] Figure 15-1. Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control register, WTCON. The valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, or 128. Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/( MCLK / (Prescaler value + 1) / Division_factor ) WTDAT & WTCNT When the watchdog timer is enabled first, the value of WTDAT (watchdog timer data register) cannot be automatically reloaded into the WTCNT (timer counter). For this reason, an initial value must be written to the watchdog timer count register, WTCNT, before the watchdog timer starts. CONSIDERATION OF DEBUGGING ENVIRONMENT When S3C44B0X is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not the current mode is the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated when the watchdog timer is expired. 15-2 S3C44B0X RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL REGISTER (WTCON) Using the watchdog Timer Control register, WTCON, you can enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The watchdog timer is used to resume the S3C44B0X restart on mal-function after power-on; if controller restart is not desired, the watchdog timer should be disabled. If the user wants to use the normal timer provided by the watchdog timer, please enable the interrupt and disable the watchdog timer. Register WTCON Address 0x01D30000 R/W R/W Description watchdog timer control Register Reset Value 0x8021 WTCON Prescaler value Reserved watchdog timer enable/disable Clock select Bit [15:8] [7:6] [5] Description the prescaler value The valid range is from 0 to (28-1) Reserved. These two bits must be 00 in normal operation. Enable or disable bit of watchdog timer. 0 = Disable watchdog timer 1 = Enable watchdog timer This two bits determines the clock division factor 00: 1/16 01: 1/32 10: 1/64 11: 1/128 Enable or disable bit of the interrupt. 0 = Disable interrupt generation 1 = Enable interrupt generation Reserved. This bit must be 0 in normal operation Enable or disable bit of watchdog timer output for reset signal 1: asserts reset signal of the S3C44B0X at watchdog time-out 0: disables the reset function of the watchdog timer. Initial State 0x80 00 1 [4:3] 00 Interrupt enable/disable Reserved Reset enable/disable [2] 0 [1] [0] 0 1 15-3 WATCHDOG TIMER S3C44B0X RISC MICROPROCESSOR WATCHDOG TIMER DATA REGISTER (WTDAT) The watchdog timer data register, WTDAT is used to specify the time-out duration. The content of WTDAT can not be automatically loaded into the timer counter at initial watchdog timer operation. However, the first time-out occurs by using 0x8000(initial value), after then the value of WTDAT will be automatically reloaded into WTCNT. Register WTDAT Address 0x01D30004 R/W R/W Description Watchdog timer data Register Reset Value 0x8000 WTDAT Count reload value Bit [15:0] Description Watchdog timer count value for reload. Initial State 0x8000 WATCHDOG TIMER COUNT REGISTER (WTCNT) The watchdog timer count register, WTCNT, contains the current count values for the watchdog timer during normal operation. Note that the content of the watchdog timer data register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the watchdog timer count register must be set to an initial value before enabling it. Register WTCNT Address 0x01D30008 R/W R/W Description Watchdog timer count Register Reset Value 0x8000 WTCNT Count value Bit [15:0] Description The current count value of the watchdog timer Initial State 0x8000 15-4 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE 16 OVERVIEW -- -- -- -- IIC-BUS INTERFACE The S3C44B0X RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line(SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C44B0X RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C44B0X, which can initiate a data transfer over the IIC-bus, is responsible for terminating the transfer. Standard bus arbitration procedure is used in this IIC-bus in S3C44B0X. To control multi-master IIC-bus operations, values must be written to the following registers: Multi-master IIC-bus control register, IICCON Multi-master IIC-bus control/status register, IICSTAT Multi-master IIC-bus Tx/Rx data shift register, IICDS Multi-master IIC-bus address register, IICADD When the IIC-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA can initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady at High Level. The Start and Stop conditions can always be generated by the master devices. A 7-bit address value in the first data byte, which is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write). Every data byte put onto the SDA line should total eight bits. The number of bytes which can be sent or received during the bus transfer operation is unlimited. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by an acknowledge (ACK) bit. 16-1 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic SCL MCLK IICCON IICSTAT 4-bit Prescaler Shift Register SDA Shift Register (IICDS) Data Bus Figure 16-1. IIC-Bus Block Diagram Note: The IIC data hold time (tSDAH) is minimum 0ns. (Refer to figure 19-52.) 1. The IIC data hold time (tSDAH) is minimum 0ns. Please check the data hold time of your IIC device. (IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.) 2. The IIC controller supports only IIC bus device (standard/ fast bus mode), not C bus device. 16-2 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE THE IIC-BUS INTERFACE The S3C44B0X IIC-bus interface has four operation modes: -- -- -- -- Master transmitter mode Master receive mode Slave transmitter mode Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in slave mode. In other words, the interface should be in slave mode before detecting a Start condition on the SDA line.(A Start condition can be initiated with a High-to-Low transition of the SDA line while the clock signal of SCL is High) When the interface state is changed to the master mode, a data transfer on the SDA line can be initiated and SCL signal generated. A Start condition can transfer a one-byte serial data over the SDA line, and a stop condition can terminate the data transfer. A stop condition is a Low-to-High transition of the SDA line while SCL is High. Start and Stop conditions are always generated by the master. The IIC-bus is busy when a Start condition is generated. A few clocks after a Stop condition, the IIC-bus will be free, again. When a master initiates a Start condition, it should send a slave address to notify the slave device. The one byte of address field consist of a 7-bit address and a 1-bit transfer direction indicator (that is, write or read). If bit 8 is 0, it indicates a write operation(transmit operation); if bit 8 is 1, it indicates a request for data read(receive operation). The master will finish the transfer operation by transmitting a Stop condition. If the master wants to continue the data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the readwrite operation can be performed in various formats. SDA SDA SCL SCL Start Condition Stop Condition Figure 16-2. Start and Stop Condition 16-3 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The number of bytes which can be transmitted per transfer is unlimited. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first. Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A "0" (Write) DATA(1Byte) AP Data Transferred (Data + Acknowledge) Write Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "0" (Write) Slave Address 2nd Byte A DATA AP Data Transferred (Data + Acknowledge) Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A "1" (Read) DATA AP Data Transferred (Data + Acknowledge) Read Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "1" (Read) Slave Address 2nd Byte A rS Slave Address 1st 7 Bits R/W A "1" (Read) DATA AP Data Transferred (Data + Acknowledge) NOTES: 1. S: Start, rS: Repeat Start, P: Stop, A: Acknowledge 2. : From Master to Slave, : from Slave to Master Figure 16-3. IIC-Bus Interface Data Format 16-4 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE SDA MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver SCL S 1 2 7 8 9 ACK 1 2 9 Byte Complete, Interrupt within Receiver Clock Line Held Low While Interrupts are Serviced Figure 16-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To finish a one-byte transfer operation completely, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master should generate the clock pulse required to transmit the ACK bit. The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received. The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA is Low during the High period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete a one-byte data transfer operation. Clock to Output Data Output by Transmitter Data Output by Receiver SCL from Master S Start Condition 1 2 7 8 9 Clock Pulse for Acknowledgment Figure 16-5. Acknowledge on the IIC-Bus 16-5 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR READ-WRITE OPERATION In the transmitter mode, after the data is transferred, the IIC-bus interface will wait until IICDS(IIC-bus Data Shift Register) is written by a new data. Until the new data is written, the SCL line will be held low. After the new data is written to IICDS register, the SCL line will be released. The S3C44B0X should hold the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into IICDS, again. In the receive mode, after a data is received, the IIC-bus interface will wait until IICDS register is read. Until the new data is read out, the SCL line will be held low. After the new data is read out from IICDS register, the SCL line will be released. The S3C44B0X should hold the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should read the data from IICDS. BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a SDA High level detects another master with a SDA active Low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line turns High. However when the masters simultaneously lower the SDA line, each master should evaluate whether or not the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because the lowering of SDA line is stronger than maintaining High on the line. For example, one master generates a Low as first address bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus because Low is stronger than High even if first master is trying to maintain High on the line. When this happens, Low(as the first bit of address) -generating master will get the mastership and High(as the first bit of address) generating master should withdraw the mastership. If both masters generate Low as the first bit of address, there should be an arbitration for second address bit, again. This arbitration will continue to the end of last address bit. ABORT CONDITIONS If a slave receiver can not acknowledge the confirmation of the slave address, it should hold the level of the SDA line High. In this case, the master should generate a Stop condition and to abort the transfer. If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then release the SDA to allow a master to generate a Stop condition. CONFIGURING THE IIC-BUS To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON register. The IIC-bus interface address is stored in the IIC-bus address register, IICADD. (By default, the IIC-bus interface address is an unknown value.) 16-6 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE FLOWCHARTS OF THE OPERATIONS IN EACH MODE The following steps must be executed before any IIC tx/rx operations. 1) Write own slave address on IICADD register if needed. 2) Set IICCON Register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output START Master Tx mode has been configured Write slave address to IICDS Write 0xF0 (M/T Start) to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Y Stop? N Write new data transmitted to IICDS Write 0xD0 (M/T Stop) to IICSTAT Clear pending bit to resume Clear pending bit The data of the IICDS is shifted to SDA Wait until the stop condition takes effect END Figure 16-6. Operations for Master/Transmitter Mode 16-7 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR START Master Rx mode has been configured Write slave address to IICDS Write 0xF0 (M/R Start) to IICSTAT The data of the IICDS (slave address) is transmitted ACK period and then interrupt is pending Y Stop? N Read new data from IICDS Write 0x90 (M/R Stop) to IICSTAT Clear pending bit to resume Clear pending bit SDA is shifted to IICDS Wait until the stop condition takes effect END Figure 16-7. Operations for Master/Receiver Mode 16-8 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS (the received slave address) N Matched? Y The IIC address match interrupt is generated Write data to IICDS Clear pending bit to resume Y Stop? N The data of the IICDS is shifted to SDA END Interrupt is pending Figure 16-8. Operations for Slave/Transmitter Mode 16-9 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR START Slave Rx mode has been configured IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS (the received slave address) N Matched? Y The IIC address match interrupt is generated Read IICDS Clear pending bit to resume Y Stop? N SDA is shifted to IICDS END Interrupt is pending Figure 16-9. Operations for Slave/Receiver Mode 16-10 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL REGISTER (IICCON) Register IICCON Address 0x01D60000 R/W R/W Description IIC-Bus control register Reset Value 0000_XXXX IICCON Acknowledge enable (1) Bit [7] Description IIC-bus acknowledge enable bit 0=Disable ACK generation 1=Enable ACK generation In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is L in the ack time. Source clock of IIC-bus transmit clock prescaler selection bit 0 = IICCLK = fMCLK /16 1 = IICCLK = fMCLK /512 IIC-Bus Tx/Rx interrupt enable/disable bit 0 = Disable interrupt, 1 = Enable interrupt IIC-bus Tx/Rx interrupt pending flag. Writing 1 is impossible. When this bit is read as 1, the IICSCL is tied to L and the IIC is stopped. To resume the operation, clear this bit as 0. 0 = 1) No interrupt pending(when read), 2) Clear pending condition & Resume the operation (when write). 1 = 1) Interrupt is pending (when read) 2) N/A (when write) IIC-Bus transmit clock prescaler IIC-Bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: Tx clock = IICCLK/(IICCON[3:0]+1) Initial State 0 Tx clock source selection Tx/Rx Interrupt enable Interrupt pending flag (2) (3) [6] 0 [5] [4] 0 0 Transmit clock value (4) [3:0] Undefined NOTES: 1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode. 2. A IIC-bus interrupt occurs 1)when a 1 -byte transmit or receive operation is completed, 2)when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. To time the setup time of IICSDA before IISSCL rising edge, IICDS has to be written before clearing the IIC interrupt pending bit. 4. IICCLK is determined by IICCON[6]. Tx clock can vary by SCL transition time. When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available. 5. If the IICON[5]=0, IICON[4] does not operate correctly. So, It is recommended to set IICCON[5]=1, although you does not use the IIC interrupt. 16-11 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR MULTI-MASTER IIC-BUS CONTROL/STATUS REGISTER (IICSTAT) Register IICSTAT Address 0x01D60004 R/W R/W Description IIC-Bus control/status register Reset Value 0000_0000 IICSTAT Mode selection Bit [7:6] Description IIC-bus master/slave Tx/Rx mode select bits: 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode IIC-Bus busy signal status bit: 0 = read) IIC-bus not busy (when read) write) IIC-bus STOP signal generation 1 = read) IIC-bus busy (when read) write) IIC-bus START signal generation. The data in IICDS will be transferred automatically just after the start signal. IIC-bus data output enable/disable bit: 0=Disable Rx/Tx, 1=Enable Rx/Tx IIC-bus arbitration procedure status flag bit: 0 = Bus arbitration successful 1 = Bus arbitration failed during serial I/O IIC-bus address-as-slave status flag bit: 0 = cleared when START/STOP condition was detected 1 = Received slave address matches the address value in the IICADD. IIC-bus address zero status flag bit: 0 = cleared when START/STOP condition was detected. 1 = Received slave address is 00000000b IIC-bus last-received bit status flag bit 0 = Last-received bit is 0 (ACK was received) 1 = Last-receive bit is 1 (ACK was not received) Initial State 0 Busy signal status/ START STOP condition [5] 0 Serial output enable Arbitration status flag Address-as-slave status flag [4] [3] 0 0 [2] 0 Address zero status flag [1] 0 Last-received bit status flag [0] 0 16-12 S3C44B0X RISC MICROPROCESSOR IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS REGISTER (IICADD) Register IICADD Address 0x01D60008 R/W R/W Description IIC-Bus address register Reset Value XXXX_XXXX IICADD Slave address Bit [7:0] Description 7-bit slave address, latched from the IIC-bus: When serial output enable=0 in the IICSTAT, IICADD is writeenabled. The IICADD value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting. Slave address = [7:1] Not mapped = [0] Initial State XXXX_XXXX MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT REGISTER (IICDS) Register IICDS Address 0x01D6000C R/W R/W Description IIC-Bus transmit/receive data shift register Reset Value XXXX_XXXX IICDS Data shift Bit [7:0] Description 8-bit data shift register for IIC-bus Tx/Rx operation: When serial output enable = 1 in the IICSTAT, IICDS is writeenabled. The IICDS value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting Initial State XXXX_XXXX 16-13 IIC-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR NOTES 16-14 S3C44B0X RISC MICROPROCESSOR IIS-BUS INTERFACE 17 OVERVIEW FEATURES -- -- -- -- -- -- -- IIS-BUS INTERFACE Many digital audio systems are introduced into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital TV sound. The S3C44B0X IIS(Inter-IC Sound) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for mini-disc and portable applications. It supports the IIS bus data format and MSB-justified data format. IIS bus interface provides DMA transfer mode for FIFO access instead of an interrupt. It can transmit or receive data simultaneously as well as transmit or receive only. IIS, MSB-justified format compatible 8/16-bit data per channel 16, 32, 48fs(sampling frequency) serial bit clock per channel 256, 384fs master clock Programmable frequency divider for master clock and CODEC clock 32 bytes (2X16) FIFO for transmit and receive Normal and DMA transfer mode 17-1 IIS-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR BLOCK DIAGRAM ADDR DATA CNTL BRFC TxFIFO SFTR RxFIFO CHNC IISDI IISDO IISCLK IPSR_A MCLK IPSR_B SCLKG IISLRCK CODECLK Figure 17-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine(BRFC) - Bus interface logic and FIFO access are controlled by the state machine. 3-bit dual prescaler(IPSR) - One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator. 16-byte FIFOs(TXFIFO, RXFIFO) - In transmit data transfer, data are written to TXFIFO, and, in the receive data transfer, data are read from RXFIFO. Master IISCLK generaor(SCLKG) - In master mode, serial bit clock is generated from the master clock. Channel generator and state machine(CHNC) - IISCLK and IISLRCK are generated and controlled by the channel state machine. 16-bit shift register(SFTR) - Parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode. TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transmit and receive FIFO. When FIFO is ready to transmit data, the FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'. When receive FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to write or read FIFOs. Serial data can be transmitted or received while CPU is accessing transmit and receive FIFOs in this way. 17-2 S3C44B0X RISC MICROPROCESSOR IIS-BUS INTERFACE DMA transfer In this mode, transmit or receive FIFO access is made by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. TRANSMIT AND RECEIVE MODE In this mode, IIS bus interface can transmit and receive data simultaneously. Because one DMA source is assigned, normal FIFO write is done in the transmit channel, and DMA receive FIFO read is done in the receive channel and vice versa. AUDIO SERIAL INTERFACE FORMAT IIS-BUS FORMAT The IIS bus has four lines, serial data input(IISDI), serial data output(IISDO), left/right channel select(IISLRCK), and serial bit clock(IISCLK); the device generating IISLRCK and IISCLK is the master. Serial data is transmitted in 2's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated(least significant data bits are set to '0') for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word at one clock period after the IISLRCK change. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. The LR channel select line indicates the channel being transmitted. IISLRCK may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The IISLRCK line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. MSB(LEFT) JUSTIFIED MSB/left justified bus has the same lines as the IIS format. It is only different with the IIS bus that transmitter always sends the MSB of the next word when the IISLRCK change. 17-3 IIS-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR LRCK LEFT RIGHT LEFT SCLK MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) SD IIS-BUS FORMAT (N=8 or 16) LRCK LEFT RIGHT SCLK MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) SD MSB-JUSTIFIED FORMAT (N=8 or 16) Figure 17-2. IIS-Bus and MSB(Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency(MCLK) can be selected by sampling frequency as shown in Table 17-1. Because MCLK is made by IIS prescaler, the prescaler value and MCLK type(256 or 384fs) should be determined properly. Serial bit clock frequency type(16/32/48fs) can be selected by the serial bit per channel and MCLK as shown in Table 17-2. Table 17-1 CODEC clock (CODECLK = 256 or 384fs) IISLRCK (fs) 8.000 KHz 256fs CODECLK (MHz) 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 KHz 16.000 KHz 22.050 KHz 32.000 KHz 44.100 KHz 48.000 KHz 64.000 KHz 88.200 KHz 96.000 KHz Table 17-2 Usable serial bit clock frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @CODECLK=256fs @CODECLK=384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit 17-4 S3C44B0X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL REGISTER (IISCON) Register IISCON Address 0x01D18000(Li/HW, Li/W, Bi/W) 0x01D18002(Bi/HW) R/W R/W Description IIS control register Reset Value 0x100 IISCON Left/Right channel index (read only) Transmit FIFO ready flag (read only) Receive FIFO ready flag (read only) Transmit DMA service request enable Receive DMA service request enable Transmit channel idle command Bit [8] [7] [6] [5] [4] [3] 0 = Left channel 1 = Right channel Description Initial State 1 0 0 0 0 0 0 = FIFO is not ready (empty) 1 = FIFO is ready (not empty) 0 = FIFO is not ready (full) 1 = FIFO is ready (not full) 0 = Request disable 1 = Request enable 0 = Request disable 1 = Request enable In Idle state the IISLRCK is inactive(pause Tx). This bit is only effective if the IIS is a master. 0 = IISLRCK is generated. 1 = IISLRCK is not generated. In Idle state the IISLRCK is inactive(pause Rx). This bit is only effective if the IIS is a master. 0 = IISLRCK is generated. 1 = IISLRCK is not generated. 0 = Prescaler disable 1 = Prescaler enable 0 = IIS disable (stop) 1 = IIS enable (start) Receive channel idle command [2] 0 IIS prescaler enable IIS interface enable (start) [1] [0] 0 0 NOTES: 1. The IISCON register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big. 17-5 IIS-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR IIS MODE REGISTER (IISMOD) Register IISMOD Address 0x01D18004(Li/W, Li/HW, Bi/W) 0x01D18006(Bi/HW) R/W R/W Description IIS mode register Reset Value 0x0 IISMOD Master/slave mode select Transmit/receive mode select Active level of left/right channel Serial interface format Serial data bit per channel Master clock(CODECLK) frequency select Serial bit clock frequency select Bit [8] [7:6] [5] [4] [3] [2] [1:0] Description 0 = Master mode (IISLRCK and IISCLK are output mode) 1 = Slave mode (IISLRCK and IISCLK are input mode) 00 = No transfer 01 = Receive mode 10 = Transmit mode 11 = Transmit and receive mode 0 = Low for left channel ( high for right channel) 1 = High for left channel ( low for right channel) 0 = IIS compatible format 1 = MSB(Left)-justified format 0 = 8-bit 1 = 16-bit Initial State 0 00 0 0 0 0 00 0 = 256fs 1 = 384fs (fs : sampling frequency) 00 = 16fs 01 = 32fs 10 = 48fs 11 = N/A (fs : sampling frequency) NOTES: 1. The IISMOD register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big. 17-6 S3C44B0X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS PRESCALER REGISTER (IISPSR) Register IISPSR Address 0x01D18008(Li/B, Li/HW, Li/W, Bi/W) 0x01D1800A(Bi/HW) 0x01D1800B(Bi/B) R/W R/W Description IIS prescaler register Reset Value 0x0 IISPSR Prescaler value A Prescaler value B Bit [7:4] [3:0] Description prescaler division factor for the prescaler A clock_prescaler_A = MCLK/ Initial State 0x0 0x0 IISPSR[3:0] / [7:4] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b Division Factor 2 4 6 8 10 12 14 16 IISPSR[3:0] / [7:4] 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Division Factor 1 - 3* - 5* - 7* - NOTES: 1. If the prescaler value is 3,5,7, the duty is not 50%. In this case, the H duration is 0.5 MCLK. 2. The IISPSR register can be accessed by byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 3. (Li/B/HW/W): Access by byte/halfword/word unit when the endian mode is Little. (Bi/B/HW/W): Access by byte/halfword/word unit when the endian mode is Big. 17-7 IIS-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR IIS FIFO CONTROL REGISTER (IISFCON) To start IIS operation, the following procedure is needed. 1) Enable the FIFO in IISFCON register 2) Enable DMA request in IISCON register 3) Enable IIS interface start in IISCON register To end IIS operation, the following procedure is needed. 1) Disable the FIFO. If you want to transmit the data remained in FIFO, you must not disable the FIFO and skip this stop 1. 2) Disable DMA request in IISCON register. 3) Disable IIS interface start in IISCON register. Register IISFCON Address 0x01D1800C(Li/HW, Li/W, Bi/W) 0x01D1800E(Bi/HW) R/W R/W Description IIS FIFO interface register Reset Value 0x0 IISFCON Transmit FIFO access mode select Receive FIFO access mode select Transmit FFO enable Receive FIFO enable Transmit FIFO data count (read only) Receive FIFO data count (read only) Bit [11] [10] [9] [8] [7:4] [3:0] 0 = Normal access mode 1 = DMA access mode 0 = Normal access mode 1 = DMA access mode 0 = FIFO disable 0 = FIFO disable Description Initial State 0 0 0 0 000 000 1 = FIFO enable 1 = FIFO enable Data count value = 0-8 Data count value = 0-8 NOTES: 1. The IISFCON register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Access by halfword/word unit when the endian mode is Little. (Bi/HW/W): Access by halfword/word unit when the endian mode is Big. 17-8 S3C44B0X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS FIFO REGISTER (IISFIF) IIS bus interface contains two 16-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 8-depth form, which allows the FIFO to handles data by halfword unit regardless of valid data size. Transmit and receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x01D18010. Register IISFIF Address 0x01D18010(Li/HW) 0x01D18012(Bi/HW) R/W R/W Description IIS FIFO register Reset Value 0x0 IISFIF FENTRY Bit [15:0] Description Transmit/Receive data for IIS Initial State 0 NOTES: 1. The IISFIF register can be accessed by halfword and word unit using STRH and LDRH instructions or short int type pointer in Little/Big endian mode. 2. (Li/HW): Access by halfword unit when the endian mode is Little. (Bi/HW): Access by halfword unit when the endian mode is Big. 17-9 IIS-BUS INTERFACE S3C44B0X RISC MICROPROCESSOR NOTES 17-10 S3C44B0X RISC MICROPROCESSOR SIO 18 OVERVIEW FEATURES -- -- -- -- -- -- -- SIO (SYNCHRONOUS I/O) The S3C44B0X SIO (synchronous IO) can interface with various types of external devices that requires serial data transfer. The SIO module can transmit or receive 8bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. 8-bit Data Buffer (SIODAT) 12-bit Prescaler (SBRDR) 8-bit Interval Counter (ITVCNT) Clock Selection Logic Serial data I/O pins (SIORXD and SIOTXD) External clock input/output pin (SIOCK) DMA run mode (auto run/flag run, SIORDY) 3-bit Counter SIOINT SIORDY SIO Control Logic SIOCK 8-bit SIO Shift Buffer MCLK 12-bit Prescaler MUX SIORXD Data Bus SIOTXD Figure 18-1. SIO Interface Block Diagram 18-1 SIO S3C44B0X RISC MICROPROCESSOR SIO NORMAL OPERATION Transmit and Receive by Serial Line Synchronously Using the serial I/O interface, 8-bit data can be exchanged by serial line. The serial output data comes through a serial input pin(SIORXD) and goes out through a serial output pin, synchronously by serial clock pin (SIOCK). After transmitting or receiving data, the SIO interrupt request is activated if a programmer enables an interrupt source. Transmitting always occurs with reception. If you want only to transmit, you may treat the received data as dummy. The transmission frequency is controlled by making the appropriate bit settings to the SIOCON and SBRDR registers. The serial interface can be operated by an internal or external clock source. If the internal clock signal is used, you can modify its frequency to adjust the baud rate data register value. Programming Procedure When a byte data is written into the SIODAT register, SIO starts to transmit if the SIO run bit is set and the transmit mode bit is enabled. To program the SIO modules, follow these basic steps: 1. 2. 3. 4. 5. 6. 7. Configure the I/O pins at port (SIOTXD, SIOCLK, SIORXD). Set SIOCON register to properly configure the serial I/O module. For interrupt generation, set the serial I/O interrupt enable bit and refer the interrupt controller to 1. If you want to transmit data to the serial buffer, write data to SIODAT. For receiving/transmitting, set SIOCON[3] to 1 to start the shift operation. When the shift operation (transmit/receive) is completed, the SIO interrupt is requested and SIODAT has the received data or dummy data. go to step 4 18-2 S3C44B0X RISC MICROPROCESSOR SIO SIO DMA OPERATION Auto Run Mode (non-hand-shaking mode) If the SIO is in the auto-run mode (non-hand-shaking mode) and the SIO transmits data using the DMA controller, SIO can wait until the transmitted data is read by the external destination device. Not using hand-shaking, the SIO must wait for a fixed interval between every 8-bit data. The interval is determined by the IVTCNT register. In the auto run mode, the SIO inserts this interval after transmitting every 8-bit data. Steps for Transmit by DMA(Refer to Fig.18-2) 1. DCNTZ[n] is cleared to 0, which allows the SIO to request DMA service. The SIO is configured properly, but the value of SIOCON[1:0] has to be 00b. DMA is configured properly. The SIO is configured as DMA transmit mode. SIOCON[3] (SIO start bit) will be ignored. The SIO automatically requests DMA service without SIO start bit(SIOCON[3]). The SIO transmits the data. Go to step 4 until DMA count is 0. DCNTZ[n] is set to 1, which stops the SIO from requesting further DMA service. 2. 3. 4. 5. 6. 7. START DCNTZ[n] = 0 Setting SIOCON (SIOCON = xx 1xxx00b) BDMA Setting SIOCON = xxxxxx 10b or xxxxxx 11b (auto start) DMAcount == 0 Y DCNTZ[n] = 1 N END Figure 18-2. SIO Transmit by DMA 18-3 SIO S3C44B0X RISC MICROPROCESSOR Steps for Receive by DMA(Refer to Fig.18-3) 1. 2. 3. 4. 5. 6. 7. DCNTZ[n] is cleared to 0, which allows the SIO to request the DMA service. The SIO is configured properly. But the value of SIOCON[1:0] has to be 00b. DMA is configured properly. The SIO is configured in DMA receive only mode. Set SIOCON[3] (SIO start bit) to start the receiving operation. The SIO requests the DMA service after 8-bit data has been received. Go to step 5 until DMA count is 0. DCNTZ[n] is set to 1, which stops the SIO from requesting further DMA service. START DCNTZ[n] = 0 Setting SIOCON (SIOCON = xxxxxx 00b) BDMA Setting SIOCON = xxxxx 110 or xxxxx 111 (manual start) DMAcount == 0 Y DCNTZ[n] = 1 N END Figure 18-3. SIO Receive by DMA 18-4 S3C44B0X RISC MICROPROCESSOR SIO SIOCLK SIORXD DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SIOTXD DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIOCON Start Bit Transmit Complete Figure 18-4. SIO Transmit/Receive Mode Timing diagram(Tx at Falling) SIOCLK SIORXD DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SIOTXD DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIOCON Start Bit Transmit Complete Figure 18-5. SIO Transmit/Receive Mode Timing diagram(Tx at Rising) 18-5 SIO S3C44B0X RISC MICROPROCESSOR Interval Time ~ ~ SIOCLK ~ ~ SIOTXD SIORXD ~~ ~~ SIOCON Start Bit DMA Condition Setting NOTE: SIO Tx is auto-start regardless of the SIOCON start bit. Transmit Complete Figure 18-6. SIO in Non-Hand-shaking Mode Timing diagram(Auto Run Mode) 18-6 S3C44B0X RISC MICROPROCESSOR SIO SYNCHRONOUS I/O INTERFACE SPECIAL REGISTERS SIO CONTROL REGISTER (SIOCON) Register SIOCON Address 0x01D14000 R/W R/W SIO control register Description Reset Value 0x00 SIOCON Clock source select Data direction Bit [7] [6] Description SIO shift clock source select bit. 0 = Internal clock, 1 = External clock This bit controls whether MSB is transmitted first or LSB is transmitted first. 0 = MSB mode, 1 = LSB mode This bit decides whether to enable the transmit operation enabled. If you want to only transmit, the received data in SIODAT will be ignored. If users want to transmit and receive, SIO supports data transmission and reception simultaneously. Users write the data transmitted in the SIODAT register and then SIO will transmit the data serially. At the same time, SIO will receive the data from an external SIO device. After the SIO transmission is completed, the contents of SIODAT, will have the received data. 0 = Receive only mode, 1 = Transmit/Receive mode Initial State 0 0 Tx/Rx selection [5] 0 Clock edge select [4] This bit determines the clock to be used for serial transmit or receive operation. 0 = falling edge clock, 1 = rising edge clock This bit determines whether the SIO functions is running or has stopped. When BDMA Tx is used, this bit should be '0'. 0 = No action 1 = Clear 3-bit counter and start shift. This bit is cleared just after writing this bit as 1. 0 SIO start [3] 0 Shift operation [2] Determines SIO shift operation 0 = Non hand-shaking mode(Auto run mode) 1 = Reserved Determines how and by what SIODATA is read/written. 00 = no operations 01 = SIO interrupt mode 10 = BDMA0 mode 11 = BDMA1 mode 0 SIO mode select [1:0] 00 18-7 SIO S3C44B0X RISC MICROPROCESSOR SIO DATA REGISTER (SIODAT) Before transmitting, the SIO data register (SIODAT) contains an 8-bit data value to be transmitted. After transmitting is completed, the SIODAT has the received data or dummy data. Register SIODAT Address 0x01D14004 R/W R/W SIO data register Description Reset Value 0x00 SIODAT SIO DATA Bit [7:0] Description This field contains the data to be transmitted or received over the SIO channel. Initial State 0x00 SIO BAUD RATE PRESCALER REGISTER (SBRDR) The baud rate prescaler register (SBRDR) determines SIO clock rate (baud rate) as follows. Baud rate = MCLK / 2 /(Prescaler value + 1) Register SBRDR Address 0x01D14008 R/W R/W Description SIO baud rate prescaler register Reset Value 0x00 SBRDR SBRDR Bit [11:0] Description This field contains the prescaler value for the baud rate Initial State 0x00 SIO INTERVAL COUNT REGISTER (IVTCNT) In the auto run mode, the SIO inserts this interval after transmitting every 8-bit data. Intervals (between 8-bit data) = MCLK / 4/ ( IVTCNT +1) Register IVTCNT Address 0x01D1400C R/W R/W Description SIO interval counter register Reset Value 0x00 IVTCNT IVTCNT Bit [7:0] Description SIO interval counter register Initial State 0x00 18-8 S3C44B0X RISC MICROPROCESSOR SIO SIO DMA COUNT ZERO REGISTER (DCNTZ) When SIO operates in DMA mode, the corresponding DCNTZ bit has to be 0 initially. When DMA terminal count is reached, the corresponding DCNTZ bit has to be set to 1. Register DCNTZ Address 0x01D14010 R/W R/W Description SIO dma count zero register Reset Value 0x0 DCNTZ DCNTZ1 Bit [1] Description 0: Enables BDMA1 service request. When this bit is 0, the SIO can request the DMA service. 1: Disables BDMA1 service request 0: Enables BDMA0 service request When this bit is 0, the SIO can request the DMA service. 1: Disables BDMA0 service request Initial State 0 DCNTZ0 [0] 0 18-9 SIO S3C44B0X RISC MICROPROCESSOR NOTES 18-10 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA 19 Symbol VDD VIN VOUT Ilatch TSTG ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 19-1. Absolute Maximum Rating Parameter DC Supply Voltage DC Input Voltage DC Input Voltage Latch-up Current Storage Temperature 3.3 V Input buffer 3.3 V buffer 200 - 40 to 125 Rating 3.6 4.6 4.6 mA o Unit V C RECOMMENDED OPERATING CONDITIONS Table 19-2. Recommended Operating Conditions Symbol VDDP VDDI VDDA TA Parameter DC Supply Voltage Internal Voltage Analog core DC Input Voltage Commercial temperature range 3.3 V I/O 2.5 V tolerant 2.5 V Core 0 to 70 Rating 3.0 to 3.6 2.3 to 2.7 2.5 5% o Unit V C 19-1 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR D.C. ELECTRICAL CHARACTERISTICS Table 19-3. Normal I/O PAD DC Electrical Characteristics VDDP = 3.3 V 0.3 V, TA = 0 to 70 C Symbol VT+ VTVH IIH Parameters Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold VT+ - VTHigh level input current Input buffer Input buffer with pull-up IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage (note) Type B6 Type B8 Type B10 Type B12 VOL Low level output voltage (note) Type B4 Type B6 Type B8 Type B10 Type B12 IDS Stop current IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 10 mA IOL = 12 mA VIN = VSS or VDD 5 uA @25 C 1.2 mA/MHz 0.4 IOH = -6 mA IOH = -8 mA IOH = -10 mA IOH = -12 mA V 2.4 VIN = VSS -10 -60 -33 10 -10 V VIN = VDDP -10 10 33 10 60 uA Condition LVCMOS LVCMOS Schmitt-trigger 0.8 0.5 0.575 0.65 uA Min Typ Max 2.0 Unit V IDD NOTE: Operating current Type B4 means 4mA output driver cell, and Type B8 means 8mA output driver cells. 19-2 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA Table 19-4. DC Electrical Characteristics (TA = 0 to 70 C) Item Normal operation Idle mode ** Slow mode(@1MHz) ** SL-Idle mode(@1MHz) ** Stop mode Symbol IDDCPU Min - Typ 60* 23* Max 80 28 - Unit mA * : 66MHz Remarks Both oscillators running, CPU static, LCD refresh active ** : Total current consumption. ITOTAL 2.1 1 5 (CPU+I/O) uA Just running 32KHz oscillator(for (@25 C) RTC), all other I/O static. 5 uA x-tal = 32.768KHz for RTC RTC consumption IRTC 2 Table 19-5. Typical current decrease percentage by CLKCON register(@66MHz) (Unit: %) Peri Current saving NOTE: IIS 1.3% IIC 1.6% ADC 0.7% RTC 0.8% UART1 3.8% SIO 0.9% ZDMA0/1 2.2% Timer012345 2.2% LCD 3.2% Total 16.7 This table includes each power consumption of each peripherals. For example, If you do not use IIS and you turned off IIS block by CLKCON register, you can save the 1.3% portion from total power consumption. 19-3 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR MCLK(MHz) 80 75 70 66 60 50 40 30 20 10 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Spec. Guranteed Area VDDCPU(V) Figure 19-1. Typical Operating Voltage/Frequency Range (VDDIO=3.3V, @Room temperature & SMDK41100 board) 19-4 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA A.C. ELECTRICAL CHARACTERISTICS tXTALCYC 1/2 VDD 1/2 V DD NOTE: The clock input from the EXTAL0 pin. Figure 19-2. EXTAL0 Clock Timing tEXTCYC tEXTHIGH tEXTLOW 1/2 VDD VIH VIH VIL VIL VIH 1/2 VDD NOTE: The clock input from the EXTCLK pin. Figure 19-3. EXTCLK Clock Input Timing 19-5 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR EXTCLK tEX2CK CLKout tEX2SCK tSCK2CK SCLK Figure 19-4. EXTCLK/CLKout/SCLK in the case that EXTCLK is used without the PLL MCLK tEX2CK CLKout tEX2SCK tSCK2CK SCLK Figure 19-5. MCLK/CLKout/SCLK in the case that EXTCLK is used with the PLL EXTCLK nRESET tRESW tMDRH OM[3:0] Figure 19-6. Manual Reset and OM[3:0] Input Timing 19-6 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA Power PLL can operate after OM[3:2] is latched. nRESET ... OSC PLL is configured by S/W first time. tOSC1 VCO is adapted to new clock frequency. Clock Disable VCO output ... t RST2RUN ... Fout MCU operates by OSC clcok. Fout is new frequency. Figure 19-7. Power-On Oscillation Setting Timing 19-7 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR OSC Wake-up Clock Disable tOSC2 VCO Output 16 OSC clocks Fout STOP mode is initiated. Figure 19-8. STOP Mode Return Oscillation Setting Timing 19-8 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA tRAD tRCD tRAD tROD tRDS tRAD tRDS tRAD tRDS tRDS tRAD tRAD tRDS tRAD tRDS tRAD tRDS tRCD tRAD tROD Tacc EXTCLK nGCSx ADDR '1' tRDS Figure 19-9. ROM/SRAM Burst READ Timing(I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=10b, ST=0, DW=16bit) DATA nBEx nOE tRDH tRDH tRDH tRDH tRDH tRDH tRDH tRDH 19-9 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR tRAD tRBED tRCD tRAD tROD tRDS tRAD tRDS tRAD tRDS tRDS tRAD tRAD tRDS tRAD tRDS tRAD tRDS tRCD tRAD tROD EXTCLK nGCSx ADDR Tacc tRBED tRDS Figure 19-10. ROM/SRAM Burst READ Timing(II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=10b, ST=1, DW=16bit) 19-10 DATA nBEx nOE tRDH tRDH tRDH tRDH tRDH tRDH tRDH tRDH S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK tHZD ADDR 'HZ' tHZD 'HZ' tHZD nOE tXnBRQS XnBREQ tXnBACKD XnBACK tXnBACKD 'HZ' tXnBRQH nGS Figure 19-11. External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0) 19-11 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR EXTCLK tRAD ADDR tRCD nGS Tacs tROD nOE tROD Tcah tRCD tRAD Tcos Tacc Toch nBE '1' tRDS DATA tRDH Figure 19-12. ROM/SRAM READ Timing (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0) EXTCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tROD Tcah tRCD tRAD Tcos Tacc tRBED Toch tRBED nBEx Tcos Toch tRDS DATA tRDH Figure 19-13. ROM/SRAM READ Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) 19-12 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD Tcos Tacc tRWBED Toch tRWBED nBEx Tcos Toch tRDD tRDD DATA Figure 19-14. ROM/SRAM WRITE Timing (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0) EXTCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD Tcos Tacc tRBED Toch tRBED nBEx Tcos Toch tRDD tRDD DATA Figure 19-15. ROM/SRAM WRITE Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1) 19-13 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR EXTCLK tRC ADDR nGCSx Tacs delayed Tacc = 6cycle Tcos sampling nWait nOE nWait DATA NOTE : The status of nWait is checked at (Tacc-1) cycle. Figure 19-16. External nWAIT READ Timing (Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0) EXTCLK ADDR nGCSx Tacc >= 2cycle nWE tWH tWS nWait tRDD DATA tRDD Figure 19-17. External nWAIT WRITE Timing (Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0) 19-14 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA Tcas Tcp Tcas Tcp Tcas Tcp Tcas Tcp Tcas Tcp Tcas Tcp Tcas Tcp tDRD tDAD Trcd EXTCLK nRASx nCASx ADDR tDOD Tcas Tcp tDRCD tDDS Figure 19-18. DRAM (EDO) Burst READ Timing (Trcd=2, Tcas=1, Tcp=1, Trp=3.5, MT=10b, DW = 16bit) DATA nOE tDDH 19-15 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR EXTCLK tHZD ADDR 'HZ' tHZD nRASx 'HZ' tHZD nCASx 'HZ' tHZD nOE tXnBRQS XnBREQ tXnBRQL 'HZ' tXnBRQH tXnBACKD XnBACK tXnBACKD Figure 19-19. External Bus Request in DRAM Cycle (Trcd=3, Tcas=2, Tcp=1, Trp=4.5) EXTCLK tDAD ADDR tDRD nRASx Trcd nCASx tDOD nOE Tcas Tcp tDOD tDRCD tDRCD Trp tDRD tDAD tDAD tDDS DATA tDDH Figure 19-20. DRAM(FP) Single READ Timing (Trcd=3, Tcas=2, Tcp=1, Trp=4.5, MT=01b) 19-16 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK tDAD ADDR tDRD nRASx Trcd nCASx tDOD nOE Tcas Tcp tDOD tDRCD tDRCD Trp tDRD tDAD tDAD tDDS DATA tDDH Figure 19-21. DRAM(EDO) Single READ Timing (Trcd=3, Tcas=2, Tcp=1, Trp=4.5, MT=10b) EXTCLK ADDR tDRD nRASx Trp tDCCD nCASx Tchr nOE/nWE '1' tDCCD tDRD Figure 19-22. DRAM CBR Refresh Timing (Tchr=4) 19-17 19-18 tDAD tDAD tDAD tDAD tDAD tDAD tDAD tDRD tDRD tDRD Trcd tDRCD tDRCD tDRCD tDRCD tDRCD tDRCD Trp Trcd tDRCD tDOD Tcas Tcp Tcp Tcas Tcas tDDS tDDS tDDS ELECTRICAL DATA EXTCLK ADDR nRASx nCASx nOE DATA tDDH tDDH tDDH Figure 19-23. DRAM(EDO) Page Hit-Miss READ Timing (Trcd=2, Tcas=2, Tcp=1, Trp=3.5, MT=10b) S3C44B0X RISC MICROPROCESSOR S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK ADDR tDRD nRASx Trp tDCCD nCASx tDCCD tDRD Figure 19-24. DRAM Self Refresh Timing EXTCLK tDAD ADDR tDRD nRASx Trcd nCASx tDWD nWE Tcas Tcp tDWD tDWCD tDWCD Trp tDRD tDAD tDAD tDDD DATA tDDD Figure 19-25. DRAM(FP/EDO) Single Write Timing (Trcd=3, Tcas=2, Tcp=1, Trp=4.5, MT=01/10b) 19-19 19-20 tDAD tDAD tDAD tDAD tDAD tDAD tDAD tDRD tDRD tDRD Trcd tDWCD tDWCD tDWCD tDWCD tDWCD tDWCD Trp Trcd tDWCD tDWD Tcas Tcp Tcp Tcas Tcas tDDD tDDD tDDD tDDD ELECTRICAL DATA EXTCLK ADDR nRASx nCASx nWE Figure 19-26. DRAM(FP/EDO) Page Hit-Miss Write Timing (Trcd=2, Tcas=2, Tcp=1, Trp=3.5, MT=01/10b) DATA S3C44B0X RISC MICROPROCESSOR S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tRAD Tcos Tacc tRDS DATA tRDH Figure 19-27. Masked-ROM Single READ Timing (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11b) EXTCLK tRAD ADDR tRCD nGCSx tRAD tRAD tRAD tRAD tRAD tROD nOE Tacc Tpac tRDS DATA tRDH tRDH tRDH tRDH tRDH Tpac tRDS tRDS Tpac Tpac tRDS tRDS Figure 19-28. Masked-ROM Consecutive READ Timing (Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11b) 19-21 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR tSCSD Trp Trcd tSBED tSCD '1' tSAD ADDR/BA tSAD A10/AP tSRD nSRAS nSCAS nGCSx SCKE tSWD Tcl tSDS Figure 19-29. SDRAM Single Burst READ Timing (Trp=2, Trcd=2, Tcl=2, DW=16bit) 19-22 DATA SCLK nBEx nWE tSDH S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK tHZD SCLK tHZD '1' 'HZ' SCKE tHZD 'HZ' ADDR/ BA tHZD A10/AP tHZD 'HZ' 'HZ' nGCSx tHZD 'HZ' nSRAS tHZD 'HZ' nSCAS tHZD 'HZ' nBEx tHZD 'HZ' nWE 'HZ' tXnBRQS XnBREQ tXnBRQL tXnBRQH XnBACK tXnBACKD tXnBACKD Figure 19-30. External Bus Request in SDRAM Timing (Trp=2, Trcd=2, Tcl=2) 19-23 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSRD nSRAS tSRD tSCSD tSCD nSCAS nBEx '1' tSWD tSWD nWE DATA 'HZ' Figure 19-31. SDRAM MRS Timing 19-24 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSRD nSRAS Trp Trcd tSCD nSCAS tSBED nBEx Tcl tSWD nWE tSRD tSCSD tSCSD tSAD tSDS DATA tSDH Figure 19-32. SDRAM Single READ Timing(I) (Trp=2, Trcd=2, Tcl=2) 19-25 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSRD nSRAS Trp Trcd tSCD nSCAS tSRD tSCSD tSCSD tSAD tSBED nBEx Tcl tSWD nWE tSDS DATA tSDH Figure 19-33. SDRAM Single READ Timing(II) (Trp=2, Trcd=2, Tcl=3) 19-26 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSRD nSRAS Trp tSCD nSCAS tSRD '1' Trc tSCSD nBEx '1' tSWD nWE DATA 'HZ' NOTE: Before executing auto/self refresh command, all banks must be idle state. Figure 19-34. SDRAM Auto Refresh Timing (Trp=2, Trc=4) 19-27 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR Tcl tSCSD Trp Trcd tSBED tSCD tSAD '1' tSAD ADDR/BA A10/AP tSRD nSRAS nSCAS nGCSx SCKE tSWD Tcl Tcl tSDS Figure 19-35. SDRAM Page Hit-Miss READ Timing (Trp=2, Trcd=2, Tcl=2) 19-28 DATA SCLK nBEx nWE tSDH S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA SCLK tCKED SCKE tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSRD nSRAS Trp tSCD nSCAS '1' tSRD '1' '1' Trc tSCSD '1' tCKED nBEx '1' tSWD '1' nWE '1' DATA 'HZ' 'HZ' NOTE: Before executing auto/self refresh command, all banks must be idle state. Figure 19-36. SDRAM Self Refresh Timing (Trp=2, Trc=4) 19-29 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSRD nSRAS Trp Trcd tSCD nSCAS tSBED nBEx tSWD nWE tSRD tSCSD tSCSD tSAD tSDD DATA tSDD Figure 19-37. SDRAM Single Write Timing (Trp=2, Trcd=2) 19-30 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA tSBED tSCD tSCSD Trp Trcd tSAD '1' tSAD ADDR/BA A10/AP tSRD nSRAS nSCAS nGCSx SCKE tSWD tSDD Figure 19-38. SDRAM Page Hit-Miss Write Timing (Trp=2, Trcd=2, Tcl=2) DATA SCLK nBEx nWE tSDD 19-31 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tACCW tCADH tXAS Figure 19-39. External DMA Timing (Handshake, Unit transfer/Block mode I) MCLK tXAS XnDREQ tCADH XnDACK tACCW tWAH Figure 19-40. External DMA Timing (Handshake, Unit transfer/Block mode II) MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR or tACCW tCADH tXAS Figure 19-41. External DMA Timing (Handshake, On The Fly mode) 19-32 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tCADH tXRS tXRS Figure 19-42. External DMA Timing (Single Step, Unit/Block/On-the-fly mode I) MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tWAS tACCW tCADH tXRH Figure 19-43. External DMA Timing (Single Step , Unit /Block/On-the-fly mode II) MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tWAS tACCW tCADH Figure 19-44. External DMA Timing (Single Step , Unit /Block/On-the-fly mode III) 19-33 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR MCLK tXRS XnDREQ tCADL XnDACK tCADH tXAD tACCR/tACCW tWAD tACCR/tACCW Figure 19-45. External DMA Timing (Demand, On The Fly mode I ) MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR/tACCW tWAD tACCR/tACCW tWAD tCADH Figure 19-46. External DMA Timing (Demand, On The Fly mode II) 19-34 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tACCW tCADH tXRS Figure 19-47. External DMA Timing (Demand, Unit transfer/Block mode I) MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tACCW tWAD tCADH Figure 19-48. External DMA Timing (Demand, Unit transfer/Block mode II) 19-35 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR tACCW tWAW tCADH Figure 19-49. External DMA Timing (Whole, Unit transfer/Block mode) MCLK tXRS XnDREQ tCADL XnDACK tXAD tACCR /tACCW tWAWO tCADH Figure 19-50. External DMA Timing (Whole, On The Fly mode) 19-36 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA tF2CDLY VFRAME tM2CDLY VM VLINE tVCLKCYC VCLK tC2DDLY VD Figure 19-51. LCD Controller Timing tSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSTARTS tSDAS tSDAH IICSDA Figure 19-52. IIC Interface Timing 19-37 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR EXTCLK tRDYIS nXWAIT tRDYIH tRDYIW tSIOCKO SIOCK tSIOTXD SIOTXD Figure 19-53. SIO Interface Transmit Timing (Rising edge clock) CODECLK IISCLK IISLRCK tLRCK IISDO tSDO IISDI tSDIS tSDIH Figure 19-54. SIO Interface Transmit Timing (Rising edge clock) 19-38 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA Table 19-6. Clock Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25 C, PLCAP = 70pf, max/min = typ 30%) Parameter External clock to CKOUT External clock to SCLK SCLK to CKOUT Crystal clock input frequency Crystal clock input cycle time External clock input frequency External clock input cycle time External clock input low level pulse width External clock input high level pulse width Mode reset hold time Reset assert time after clock stabilization Power-on oscillation setting time STOP mode return oscillation setting time the interval before CPU runs after nRESET is released. Symbol tEX2CK tEX2SCLK tSCLK2CK fXTAL tXTALCYC fEXT tEXTCYC tEXTLOW tEXTHIGH tMDRH tRESW tOSC1 tOSC2 tRST2RUN Min - - - 6 50 1 15.1 5 5 3.0 4 - - - Typ 12 8 4 - - - - - - - - 4096 4096 132 Max - - - 20 166.7 66 1000 - - - - - - - Unit ns ns ns MHz ns MHz ns ns ns ns MCLK MCLK MCLK MCLK 19-39 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR Table 19-7. ROM/SRAM Bus Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf, max/min = typ 30%) Parameter ROM/SRAM Address Delay ROM/SRAM Chip select Delay ROM/SRAM Output enable Delay ROM/SRAM read Data Setup time. ROM/SRAM read Data Hold time. ROM/SRAM Byte Enable Delay ROM/SRAM Write Byte Enable Delay ROM/SRAM output Data Delay ROM/SRAM external Wait Setup time ROM/SRAM external Wait Hold time ROM/SRAM Write enable Delay Symbol tRAD tRCD tROD tRDS tRDH tRBED tRWBED tRDD tWS tWH tRWD Min - - - - - - - - - - - Typ 12 11 11 1 5 13 14 14 1 5 14 Max - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns 19-40 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA Table 19-8. Clock Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf, max/min = typ 30%) Parameter DRAM Address Delay DRAM Row active Delay DRAM Read Column active Delay DRAM Output enable Delay DRAM read Data Setup time DRAM read Data Hold time DRAM Write Cas active Delay DRAM Cbr Cas active Delay DRAM Write enable Delay DRAM output Data Delay Symbol tDAD tDRD tDRCD tDOD tDDS tDDH tDWCD tDCCD tDWD tDDD Min - - - - - - - - - - Typ 12 11 11 12 1 5 14 12 13 14 Max - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns Table 19-9. Memory Interface Timing Constants (VDDP :3.3V, VDDI:2.5V, Ta = 25C, PLCAP = 70pf, max/min = typ 30%) Parameter SDRAM Address Delay SDRAM Chip Select Delay SDRAM Row active Delay SDRAM Column active Delay SDRAM Byte Enable Delay SDRAM Write enable Delay SDRAM read Data Setup time SDRAM read Data Hold time SDRAM output Data Delay SDRAM Clock Eable Delay Symbol tSAD tSCSD tSRD tSCD tSBED tSWD tSDS tSDH tSDD Tcked Min - - - - - - - - - - Typ 4 4 4 4 5 5 4 0 8 5 Max - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns 19-41 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR Table 19-10. External Bus Request Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf, max/min = typ 30%) Parameter eXternal Bus Request Setup time eXternal Bus Request Hold time eXternal Bus Ack Delay HZ Delay Symbol tXnBRQS tXnBRQH tXnBACKD tHZD Min - - - - Typ. 2 5 15 7 Max - - - - Unit ns ns ns ns Table 19-11. DMA Controller Module Signal Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf, max/min = typ 30%) Parameter eXternal Request Setup eXternal Acknowledge Setup aCcess to Ack Delay when Low transition aCcess to Ack Delay when High transition eXternal Acknowledge Delay Width Acknowledge when Handshake mode Width of Acknowledge high when Whole mode Width of Acknowledge high when Whole and OTF mode Width Ack of Single eXternal Request Hold Width of Acknowledge when Demand mode Symbol tXRS tXAS tCADL tCADH tXAD tWAH tWAW tWAWO tWAS tXRH tWAD Min - - - - 2 0 2 0 3 0 0 Typ. 3 3 11 9 - - - - - - - Max - - - - - - - - - - - Unit ns ns ns ns MCLK MCLK MCLK MCLK MCLK MCLK MCLK 19-42 S3C44B0X RISC MICROPROCESSOR ELECTRICAL DATA Table 19-12. LCD Controller Module Signal Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf) Parameter VCLK cycle time VCLK to VD delay time VM to VCLK delay time VFRAME to VCLK delay time Symbol tVCLKCYC tC2DDLY tM2CDLY tF2CDLY Min 4 - 4 - Typ. - - - - Max - 3 - 3 Unit MCLK ns MCLK ns Table 19-13. IIS Controller Module Signal Timing Constants (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf) Parameter IISLRCK delay time IISDO delay time IISDI input setup time IISDI input hold time CODEC clock frequency Symbol tLRCK tSDO tSDIS tSDIH tCODEC Min 0.5 0.4 7.9 0.3 1/16 Typ. - - - - - Max 5.7 2.5 - - 1 Unit ns ns ns ns fIIS_BLOCK Table 19-14. IIC BUS Controller Module Signal Timing (VDDP: 3.3V, VDDI: 2.5V, Ta = 25C, PLCAP = 70pf) Parameter SCL clock frequency SCL high level pulse width SCL low level pulse width Bus free time between STOP and START START hold time SDA hold time SDA setup time STOP setup time NOTE: Symbol fSCL tSCLHIGH tSCLLOW tBUF tSTARTS tSDAH tSDAS TstOPH Min - std. 4.0 fast 0.6 std. 4.7 fast 1.3 std. 4.7 fast 1.3 std. 4.0 fast 0.6 std. 0 fast 0 std. 250 fast 100 std. 4.0 fast 0.6 Typ. - - - - - - - - Max std. 100 fast 400 - - - - std. - fast 0.9 - - Unit KHz us us us us us ns us Std. means Standard Mode and fast means Fast Mode. 19-43 ELECTRICAL DATA S3C44B0X RISC MICROPROCESSOR NOTES 19-44 S3C44B0X RISC MICROPROCESSOR MECHANICAL DATA 20 MECHANICAL DATA PACKAGE DIMENSIONS 26.00 0.20 0-7 24.00 0.10 + 0.073 0.127 - 0.037 26.00 0.20 24.00 0.10 160-LQFP-2424 0.08 MAX #160 #1 0.50 + 0.07 0.20 - 0.03 0.08 MAX (2.25) 0.05-0.15 1.40 0.05 1.60 MAX NOTE: Dimensions are in millimeters. Figure 20-1. 160-LQFP-2424 Package Dimensions 0.45-0.75 20-1 MECHANICAL DATA S3C44B0X RISC MICROPROCESSOR Figure 20-2. 160-FBGA-12.0x12.0 Package Dimensions 1 20-2 S3C44B0X RISC MICROPROCESSOR MECHANICAL DATA Figure 20-3. 160-FBGA-12.0x12.0 Package Dimensions 2 NOTE: To get more specific information for testing the FBGA/TQFP package using JTAG, Please contact us. 20-3 MECHANICAL DATA S3C44B0X RISC MICROPROCESSOR NOTES 20-4 |
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